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Accessing analog voltages in hierarchy from Verilog AMS

amacSS

Hi, I'm trying to access a voltage outside a Verilog AMS module; is it possible?

I tried with V(net) without success; the net is at top level.

Also V(TESTBENCH_NAME.net) does not work.

Using $cds_get_analog_value(net) or $cds_get_analog_value(TESTBENCH_NAME.net) also results in:

ERROR (VALUEFETCH-001) $cds_get_analog_value() failed: No hierarchical name specified.

Any idea?

  • Andrew Beckett

    If using $cds_get_analog_value or $cgav then you need to put the name in quotation marks "TESTBENCH_NAME.net" for example. I think you should be able to use a top-level name from a lower scope. This is described in How to use cds_get_analog_value in AMS Designer?

    Andrew

  • amacSS
    in reply to Andrew Beckett

    I tried also with quotes but get a different error:

    ERROR (VALUEFETCH-004) $cds_get_analog_value() failed: Failed to fetch the value of TOP_SIM_TM2.TBUF. Please check for correctness the name of the item, whether the item whose value is being requested is owned by the analog solver and whether the specified quantity is valid for the item.

    The examples you link always get a net on sub-cells, so I'm wondering if this is a constraint.

    In my case the verilog-ams is not the top cell.

  • Saloni Chhabra
    in reply to amacSS

    Are you sure TOP_SIM_TM2.TBUF falls in electrical/analog domain? Perhaps you can first run a simulation saving this net and plot its value to make sure it is analog.

    Regards,

    Saloni

  • amacSS
    in reply to Saloni Chhabra

    Yes, it is saved and correctly shown as an analog waveform.

    In fact the purpose was to measure it at specific times in order to automate what is now a visual check.

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