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How to read in a text file separated by delays in Verilog A. They delays are relative and to be read from the text file?

Nisharg shah

I have defined a Verilog A code to read in a text file containing text instructions and I process the text instructions to convert the real values of signal to an analog bus equivalent. 

My code works for just the first instruction, but It doesn't work for the other instructions which come in after the first line in text file. The example input instruction file is as follows:

instruction text file:

0.1msec write SET_VIN1 5 V
0.3msec write SET_VIn2 2 V

The code that I have so far gives the output as follows:

nothing happens until time 0.1msec, at 0.1msec, 8 bits of SET_VIN1 gets 11111111 with 1 represented as VDD and 0 as VSS, but the 2nd instruction doesn't get processed at all.

Required output:

@ time t = 0.1msec SET_VIN1 should get 11111111

@ time t = 0.4msec SET_VIN2 should get 01100110 The time on 2nd instruction is relative to the first instruction.

My implementation:

`include "constants.h"
`include "disciplines.h"
module analog_conversion( set_vin1,
                                              set_vin2,
                                              VDD
                                            );
electrical  VDD;
electrical [7:0] set_vin1;
electrical [7:0] set_vin1;

integer pntr,file,test_file,final_test_file;
integer cnt;
real wait_time;
integer byte_count;
string unit;
string line;
string operation;
string loc;
real loc_value;
real vrefp, vrefn;
integer dout;

analog
    begin
        @(initial_step)
            begin
                pntr = $fopen("instruction.txt", "r");
                $display("pntr is :",pntr);
                test_file = $fgets(line,pntr);
                final_test_file = $sscanf(line,"%gmsec %s %s %g %s\n",wait_time,operation,loc,loc_value,unit);
            end        
         @(timer(wait_time))
                begin          
                    case(loc)
                        "SET_VIN1":
                            begin
                                vrefp = 5;
                                vrefn = 0;
                                if((vrefp) > (vrefn))
                                    begin
                                        dout = min(255, max(0, 256*((loc_value) - (vrefn))/((vrefp) - (vrefn))));
                                    end
                                else
                                    begin
                                        dout = 0;
                                    end    
                                $display("the dout is: ",dout);        
                            end
                        "SET_VIN2":
                            begin
                                vrefp = 5;
                                vrefn = 0;
                                if((vrefp) > (vrefn))
                                    begin
                                        dout = min(255, max(0, 256*((loc_value) - (vrefn))/((vrefp) - (vrefn))));
                                    end
                                else
                                    begin
                                        dout = 0;
                                    end    
                                $display("the dout is: ",dout);        
                            end
                                           
                    endcase
                end
           
            case(loc)
                "SET_VIN1":
                    begin
                        for (j = 0; j <=7; j = j+1)
                            begin
                                V(set_vin1[j]) <+(dout & (1<<j) ? 1 : 0)*V(VDD);
                                //$display("Voltage at the output[%d] is:",j,V(setVOUT1[j]));
                            end
                    end

                "SET_VIN2":
                    begin
                        for (j = 0; j <=7; j = j+1)
                            begin
                                V(set_vin2[j]) <+(dout & (1<<j) ? 1 : 0)*V(VDD);
                                //$display("Voltage at the output[%d] is:",j,V(setVOUT1[j]));
                            end
                    end
            endcase




       
        V(VDD)<+transition(1.8);  
                 
    end
endmodule

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