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Cadence Virtuoso Schematic: Input pin goes to 2 different nets

Piash

I have a silly problem regarding input pins connecting to 2 different nets of a circuit in cadence virtuoso. Due to non-sharable agreement, I cannot share the actual circuit. But I can provide simple block diagram. This is the following non-overlapping clock circuit. I am concerned with 4 input pins which selects the nets in the diagram and select the specific MUX. The idea is when externally I0 input pin is selected then circuit should select both I0_M1 of MUX 1 and also I0_M2 of MUX 2, I1 input pin is selected then circuit should select both I1_M1 of MUX 1 and also I1_M2 of MUX 2 and so on.

As, the internal circuit cannot be changed. I cannot connect I0 pin to both I0_M1 and I0_M2, I1 pin to both I1_M1 and I1_M2 and so on because in that case I0_M1 and I0_M2 are connected or I1_M1 and I1_M2 will be connected.

Now I have implemented the circuit in Cadence virtuoso. Now stuck with the following problem. How can I implement the connection suppose when I0 input pin is selected then circuit should select both I0_M1 of MUX 1 and also I0_M2 of MUX 2? Do I need extra circuitry from I0 pin to the corresponding nets (I0_M1 & I0_M2) to connect to the MUXs? Or is there any other simple way? Also to be noted that input pins I0 - I3 can not be changed to any other input pins.

  • Dear Piash,

    Piash said:
    How can I implement the connection suppose when I0 input pin is selected then circuit should select both I0_M1 of MUX 1 and also I0_M2 of MUX 2? Do I need extra circuitry from I0 pin to the corresponding nets (I0_M1 & I0_M2) to connect to the MUXs? Or is there any other simple way?

    Perhaps I am totally misunderstanding the description of your issue - and I apologize if I am! However, after reading your post a few times, I "think" I might understand. In your schematic diagram, I don't see the select inputs to your two multiplexers (both of which are labeled "MUX"). With four inputs to each MUX, I do not see a 2 bit bus whose binary value chooses one of the form inputs as its output? If you neglected showing the select pins to each multiplexer, then it is only necessary to use the same select signal bus for each multiplexers to provide outputs of Ix_M1 from your top MUX and Ix_M2 from your bottom MUX. I have tried to illustrate this in Figure 1.

    Hopefully, I understood your question and circuit correctly!

    Shawn

    Figure 1

  • in reply to ShawnLogan

    Dear ,

    Thanks for your answer and effort. You got it perfectly. Actually, that was an unintentional mistake not to draw the 2 select bits. Now my problem is implementing the 2 select ports to 4 inputs (I0 - I3) in the circuit. Data input ports (I0_M3 to I3_M1 / I0_M2 to I0_M3) are connected to the mux circuit input. Now the select inputs have 2 ports each ports in also inverted inside the mux circuit to have inverted signals for the combination of selections. Now how can I implement the 4 selection ports inside mux ( from sel_0 & sel_1) and connect it to the ports I0 - I3 ?

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