Transient simulation - varying accuracy

Patrick,

First of all, do not set minstep - this is almost never a good idea (about the only thing it's useful for is to try to get around some nasty modelling problem where the time step collapses but even then it's a last resort rather than something you should ever use in normal usage). It's not (AFAIK) supported as a dynamic parameter anyway.

There is the ability to do scoped reltol - so you can have the reltol looser based on a specific sub circuit, but I rather doubt this would help you.

The best approach is probably to turn off the supply for the ring oscillator and only turn it on late in the simulation.

Andrew

Dear Patrick,

patschouly said:

I'm simulating two circuits together that have very different time resolution requirements (ms vs. ns). I need the first circuit to settle, which takes up to 100 ms. During this time, I'm happy just to completely ignore the other one (a ring oscillator). Is there a way to do this?

Andrew Beckett said:

The best approach is probably to turn off the supply for the ring oscillator and only turn it on late in the simulation.

Andrew's suggestion of disabling the ring oscillator (if possible) is a good idea, but without a more detailed view of the two subcircuits and their relationship, may not solve your problem.

For example, the two circuits with significant time constant differences that come to mind as I read your post is a voltage regulator and a VCO whose supply voltage is the output of the voltage regulator. The voltage regulator's dominant time constant (us or milliseconds) is much greater than that of a ring VCO (a few nanoseconds).

Although disabling the VCO output at the start of the simulation will allow the simulator time step to be set by the accuracy requirement and voltage regulator time constant, once you enable the VCO, this will induce a current step from the voltage regulator output. The transient induced by the current step will settle at the time constant of the regulator and hence you are not avoiding the significant difference in time steps required for the two circuits. The type of system you are trying to simulate is more generally referred to as a "stiff set of differential equations". Given that the VCO is periodic, what I might suggest are the following. Perhaps one or more of these are relevant Patrick...

1. In lieu of running a transient simulation only, perform a pss analysis and allow spectre to estimate the periodic solution (including your regulator). The two circuit entities do not have to fully reach their steady-state operating conditions for a pss analysis to converge on a steady-state solution.

2. Remove the regulator from the circuit and use a model consistent with the interaction between the two you are studying.

a. I you are studying the VCO frequency sensitivity to its supply voltage (typically called Kvdd), use a DC source to model the regulator,

b. If you are studying the post-layout performance of the regulator and the VCO, use a config view and substitute the schematic view of the regulator for its extracted view to reduce netlist size and expedite simulation time.

c. If you are trying to assess the impact of regulator noise on phase noise of the VCO, this can be very accurately estimated by knowledge of the VCO Kvdd and the small-signal noise of the regulator. I can provide additional details if this is relevant Patrick.

Shawn

Thank you Andrew and Shawn, those are very valuable suggestions. They are mostly applicable in my case, but I'd still like to know if there is a more general solution, as I still might run into some problems here. To be more precise, I'm simulating a power-on reset, which uses a small current to charge a large capacitor, then followed by a schmitt trigger.  This reset time might not be large enough for some applications, so this first reset is connected to a digital counter. Only when the counter reaches a certain value, the actual real circuit reset is released. The counter is clocked by the ring oscillator. Since the first reset time varies a lot across corner, I can't really say when the oscillator has to be enabled. Of course, it would be possible to enable the oscillator with the reset signal, maybe that's the easiest way to solve this. But I am not really a fan of increasing circuit complexity only to solve simulation problems.

Still, your suggestions already helped me a lot to simulate this circuit.

Kind regards,

Patrick

Dear Patrick,

Thank you for supplying the additional information on your actual simulation - it is most helpful! It tried to create a simple block diagram to better explain a thought or two to you. I may not have the exact implementation and also have a  couple of questions (i.e., is the charging capacitor discharged periodically after the schmitt trigger changes logic state?, is there a divider after the VCO to drive the counter?)

In any case, I have also encountered situations where added circuitry is required to expedite or facilitate a set of simulations. However, in many cases the added circuitry is necessary for circuit test purposes as it is also a time sensitive application. Hence, you might want to consider how the ATE will test your power-up reset without requiring the time for the PVT dependent current to charge up the large capacitor.

Towards that end, a couple of possible means of reducing the simulation time and possible test time in addition to using the first reset to enable your ring oscillator is shown in Figure 1. Basically, if you include a second charging capacitor,C2, in parallel with your original large capacitor C1 and only switch in capacitor C1 when the normal delay is required, you can reduce the reset time significantly. Alternately, or in addition, if you include a second current source I1 whose value is much greater than your original current source I0 (or make your current source programmable in value), the time to charge the capacitor will be significantly less.

Anyway, I thought I might pass these your way in the hope they provide some added insights to you!

Shawn

Figure 1

Dear Patrick,

Thank you for supplying the additional information on your actual simulation - it is most helpful! It tried to create a simple block diagram to better explain a thought or two to you. I may not have the exact implementation and also have a  couple of questions (i.e., is the charging capacitor discharged periodically after the schmitt trigger changes logic state?, is there a divider after the VCO to drive the counter?)

In any case, I have also encountered situations where added circuitry is required to expedite or facilitate a set of simulations. However, in many cases the added circuitry is necessary for circuit test purposes as it is also a time sensitive application. Hence, you might want to consider how the ATE will test your power-up reset without requiring the time for the PVT dependent current to charge up the large capacitor.

Towards that end, a couple of possible means of reducing the simulation time and possible test time in addition to using the first reset to enable your ring oscillator is shown in Figure 1. Basically, if you include a second charging capacitor,C2, in parallel with your original large capacitor C1 and only switch in capacitor C1 when the normal delay is required, you can reduce the reset time significantly. Alternately, or in addition, if you include a second current source I1 whose value is much greater than your original current source I0 (or make your current source programmable in value), the time to charge the capacitor will be significantly less.

Anyway, I thought I might pass these your way in the hope they provide some added insights to you!

Shawn

Figure 1