Maestro config sweep causing changes netlisting for bus "<"

Dear brianbranch,

brianbranch said:

When I run a config sweep that removes a cell that contains saved nodes, the save portion of the input.scs changes the naming syntax of buses from "net_to_be_saved_1" to "net_to_be_saved<1>". This creates the following error:

 ERROR (SFE-874): "input.scs" 31435: Cannot run the simulation because the syntax error `Unexpected operator ">". Expected end of file or end of line' was encountered at line 48. Correct the syntax error and rerun the simulation.

Is there a way to fix this issue?

Did you happen to read this note on the Cadence On-line support site?

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V000009EW0jUAG&pageName=ArticleContent

The article notes that this error can occur for busses when the terminal mapping of the CDF is not defined correctly.

Specifically, from the example from the article:

If you have terminals A<3> , A<2>, A<1>, A<0> or A<3:0> on the symbol, then following should be the termOrder and termMapping:

termOrder => "A<3>" "A<2>" "A<1>" "A<0>"
termMapping => nil A\<0\> "\\:A\\<0\\>" A\<1\> "\\:A\\<1\\>" A\<2\> "\\:A\\<2\\>" A\<3\> "\\:A\\<3\\>"

Does help at all brianbranch?

Shawn

Whilst the article that Shawn refers to is relevant to netlisting of bus terminals, I don't think it's necessarily only going to show up when using config sweeps. Also, it's specifically about bus terminals, whereas I think (assuming your terminology was correct) you were talking about nodes/nets not terminals.

First of all, please specify which IC sub-version you're using - you mentioned that it was "6.1.8-64b" which accounts for almost 4 years of different versions - there have been a major release and 26 hotfix versions in that time, so the issue you are talking about may no longer be an issue. The full sub-version can be seen in the Help→About menus.

Secondly, the mapping of a bus index to "net_to_be_saved_1" is not the standard behaviour. Normally it would get mapped:

save op I0.int\<4\> 

I do see the mapping if I switch back to the "old" (very old) mapping (non-nmp) as described in this article: Name mapping for spectre netlisting has changed in IC61X . Then I get:

save op I0.int_4 

for the view where the bus net exists, but for the view where it doesn't exist, the save ends up being the syntax with the escaped angle brackets.

Please show what you get by typing these in the CIW:

envGetVal("asimenv" "mappingMode")
hnlSpectreMapNetInName

I suspect that putting:

envSetVal("asimenv" "mappingMode" 'string "nmp")

in your .cdsinit would fix this.

My tests were performed in IC6.1.8-64b.500.26 (i.e. the latest available ISR/hotfix).

Andrew

Hi Andrew

I am using IC6.1.8-64b.500.4. You are right, I was talking about nets. Sorry for the confusion Shawn.

Andrew, below are the results of the CIW commands you posted:

envGetVal("asimenv" "mappingMode")
"oss"
hnlSpectreMapNetInName
((">" "")
("<" "_")

...

After adding to the .cdsinit and restarting cadence, I get the following from those CIW commands:

envGetVal("asimenv" "mappingMode")
"nmp"
hnlSpectreMapNetInName
*Error* toplevel: undefined variable - hnlSpectreMapNetInName

When running the maestro sweep, I still get the same error described above and the input.scs still shows the "<" being converted to "_" for the case where I do not sweep the config. Is it possible the maestro setup has an internal name mapping setting?

Thanks.

You might need to go over the test name and do Right Mouse→Netlist→Recreate - if that looks OK, then it should (I think) update the basis of the incremental netlister so that's OK. My guess is that the incremental netlister has already netlisted the blocks in question and so doesn't renetlist them unless forced.

Andrew

It works now. Thank you for your help.