How To achieve pulse supply voltage with four different levels of voltage

This doesn't really need Verilog-A. A PWL source should be able to do this - I simplified it by avoiding the need for separate TF and TR parameters, as otherwise you would need the time breaks to be dependent upon whether it is rising or falling. That could be done - more in a moment. However, assuming you're consolidating it into one "TRF" parameter, something like this:

You can also make them periodic - and you can alter the number of time-voltage pairs.

Potentially if you wanted to have a rise/fall parameter separate, then you could change (for example) T1+TRF to be T1+(V1>V0?TR:TF) - I think that would do it (I didn't test it).

Andrew

Thank Andrew you it worked.

I have one more question

I  want to  use this output of 4-level voltage generator to  be  as input to  4 pulse supplies  (P0 P1 P2 P3) each one of them just gives  one pulse when it is triggered by  the specified input voltage level of 4-level voltage generator

let's say  P0 gives one pulse of V=1v for period T when and only its input level of V1 then back to  zero  , and  P1 gives one pulse  its input level of  V2 then back to  zero .P2 gives one pulse  when and only its input level of V3 then back to  zero .P3 gives one pulse  when and only its input level of  V3 then back to  zero.what  types of sources can I  use to do so. I am thinking of using vcvsp .

That's going to be far simpler to do with a VerilogA model; it would start getting a bit messy to do with vcvs or pvcvs, I think.

Sorry, don't have the bandwidth to put this together, test and show an example (it's not quite like the SKILL example I just shared which I can do in my sleep - I need to create a test example, write the model, simulate it to test it works - not enough time to do that before going on holiday).

Regards,

Andrew

Dear Omar,

Omar Ghazal said:

I  want to  use this output of 4-level voltage generator to  be  as input to  4 pulse supplies  (P0 P1 P2 P3) each one of them just gives  one pulse when it is triggered by  the specified input voltage level of 4-level voltage generator

...

Omar Ghazal said:

I am thinking of using vcvsp .

Unless I am misunderstanding your need Omar, I do not think a vcvs (or vcvsp) will accomplish what you need. These are all linear sources and your need is for a non-linear source. A linear source can be characterized by a linear equation, but in your case, the gain effectively goes to infinity when the input to one of the pulse supplies (P0, P1, P2, or P3) transitions from one of the four voltage levels you define (V1, V2, V3, and V4) to 0.

What I might suggest is that you create each pulse generator using an ideal veriloga based comparator followed by an instance of an ideal veriloga based single shot. Both exist in the adhl library. An example of the test bench I created to attempt to illustrate what I hope is your need and its response are shown at URL:

https://www.dropbox.com/s/fjvmm5qkozmni9y/test_pulse_gen_summary_080222v1p0.pdf?dl=0

The simple input.scs file is attached to this post. I hope this helps Omar!

Shawn

// Point Netlist Generated on: Aug  2 14:51:54 2022
// Generated for: spectre
// Design Netlist Generated on: Aug  2 14:51:54 2022
// Design library name: sdd5e_TB
// Design cell name: test_pulse_gen
// Design view name: schematic
simulator lang=spectre
global 0
parameters vpulse_mV=500 cload_pf=5 pulse_width_ns=12 ttran_ns=0.1 \
    vdda_val=0.8 vthreshold_mV=250 period_vpulse_ns=50
include "$CDS_WORKAREA/src/simCases/apdser_spectre_model.scs" section=typicalmid
parameters  sorting_num=1e9 area_predictn_core=1e7 area_predictp_core=1e7 \
    area_predictn_io=1e6 area_predictp_io=1e6

// Library name: sdd5e_TB
// Cell name: test_pulse_gen
// View name: schematic
V0 (vin vssa) vsource type=pwl wave=[ 0 0 1n 0 \
        ((1+period_vpulse_ns/2)*1e-09/2) (vpulse_mV*1e-03) \
        ((5+1+period_vpulse_ns/2)*1e-09) (vpulse_mV*1e-03) \
        ((10+5+1+period_vpulse_ns/2)*1e-09) (vpulse_mV*1e-03) \
        ((10+5+1+period_vpulse_ns)*1e-09) 0 ]
pulse_gen (vcomp_out vout) single_shot pulse_width=pulse_width_ns*1e-09 \
        vlogic_high=vdda_val vlogic_low=0 vtrans=vdda_val/2 \
        tdel=5*ttran_ns*1e-09 trise=ttran_ns*1e-09 tfall=ttran_ns*1e-09
comparator (vin vref vcomp_out) comparator sigout_high=vdda_val \
        sigout_low=0 sigin_offset=0 comp_slope=-1e9
V2 (vssa 0) vsource dc=0 type=dc
V1 (vref vssa) vsource dc=vthreshold_mV*1e-03 type=dc
C0 (vout vssa) capacitor c=cload_pf*1e-12
simulatorOptions options psfversion="1.4.0" reltol=1e-3 vabstol=1e-6 \
    iabstol=1e-12 temp=25 tnom=25 scalem=1.0 gmin=1e-12 rforce=1 \
    nportirfiledir="/project/sdd5e/users/smlogan/cds/.cadence/mmsim" \
    maxnotes=5 maxwarns=5 digits=5 cols=80 pivrel=1e-3 \
    sensfile="../psf/sens.output" checklimitdest=psf \
    disk_check_autoresume=yes 
tran tran stop=100n errpreset=moderate write="spectre.ic" \
    writefinal="spectre.fc" annotate=status maxiters=5 \
    saveperiodhistory=yes 
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
save vin vref vcomp_out vout vssa 
saveOptions options save=selected subcktoppoint=yes
ahdl_include "/tools/virtuoso/20.1.ISR26/tools/dfII/samples/artist/ahdlLib/single_shot/veriloga/veriloga.va"
ahdl_include "/tools/virtuoso/20.1.ISR26/tools/dfII/samples/artist/ahdlLib/comparator/veriloga/veriloga.va"

Thank you Shawn . I will give a try 

Thanks ,  Andrew