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Community Custom IC Design setting temperature by veriloga via cds_set_temperature...

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setting temperature by veriloga via cds_set_temperature and make it work for stb analysis

StephanWeber
StephanWeber over 2 years ago

Hi,

according the Cadebnce suggestions I made such kind of VA module:

// VerilogA for bhvLib, vctemp, veriloga

`include "constants.vams"
`include "disciplines.vams"

module vctemp(in);
 parameter real tupdate  = 10u from (1p:1];
input in;
electrical in;

real temper=0;

analog begin

@(timer(tupdate,tupdate)) begin
  temper = V(in);
  $cds_set_temperature(temper);
end
end
endmodule

Without timer I got unfortunately a crash with spectre. But with timer the DC and tran analysis with a thermal RC network (generating Vin) works fine (just a bit slow).

However, I also want to check the stability for my thermal loop, and this does not work well, because the loop gain plots are very noisy with the VA cell in my testbench.

I believe, if we had a continous T update according the the input voltage, stb would work fine, but as mentioned then I got the crashes.

I made an alternative modeling without verilogA and using a vcvs with -2mV//K to mimic the bipolar T-sensor behavior, and that works well also in stb analysis. But it would be great to make stb working also together with that VA module.

Does anybody has an idea to make cds_set_temperature work in stb (or AC) analysis?

Bye Stephan

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  • ShawnLogan
    ShawnLogan over 2 years ago

    Dear Stephan,

    StephanWeber said:
    Does anybody has an idea to make cds_set_temperature work in stb (or AC) analysis?

    My limited understanding of the use of $cds_set_temperature from the verilog-A reference manual:

    set_temperature_function ::=
        $cds_set_temperature(expression)

    expression should be a real-type expression that represents the temperature to be set in degree Celsius. You can use variables and parameters in the expression.

    When $cds_set_temperature() is called during simulation, the simulation behavior changes in a way similar to dynamic parameter simulation.

    Hence, its use appears to be designed to be an alternative to using the temperature as a dynamic parameter in a transient simulation. This makes sense as you noted without a timer in your veriloga code, the simulation did not complete successfully. 

    As such, have you explored using a timer in your veriloga code to change the temperature at specific times in a transient simulation. For example, you might change the temperature every 1 ms to use an arbitrary example. Include a stability analysis (acnames = stb) at actimes of, for example, 0.50 ms 1.50 ms 2.50 ms. If you perform a transient simulation for 3 ms, the temperature will change from its value at time = 0, 1 ms, 2 ms, and 3 ms. A stability analysis will be performed at the DC operating point at simulation times 0.50 ms, 1.50 ms, and 2.50 ms. The acname and actimes parameters are set in the Transient simulation GUI under the Options-> Output tab as shown in Figure 1.

    Do you think this might help you? Without knowing all the details of your circuit and application, I am not sure if it will address your question, but thought I would at least pass the thought by you StephanWeber.

    Shawn

    Figure 1

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  • StephanWeber
    StephanWeber over 2 years ago in reply to ShawnLogan

    Hi Shawn,

    the problem with stb analysis is that it looks incorrect, both for stb in general, and also for stb used in actimes and acnames. I believe it is a deeper problem.

    Bye Stephan

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  • Andrew Beckett
    Andrew Beckett over 2 years ago in reply to StephanWeber

    You should contact support. I'm not sure this will work anyway - changing the temperature should only be done discretely and in small steps as is likely to cause major convergence difficulty otherwise.

    Andrew

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  • Andrew Beckett
    Andrew Beckett over 2 years ago in reply to StephanWeber

    You should contact support. I'm not sure this will work anyway - changing the temperature should only be done discretely and in small steps as is likely to cause major convergence difficulty otherwise.

    Andrew

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