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STT-PMA MTJ

Aswathyn

I want to build NAND/AND gate using LIM architecture with MTJ/CMOS. so i first build the write circuitry . when i calculate the power it is in Megawatt. Normally I saw power in nano or micro watt. I am using STT PMA MTJ model from spin library. 

Vdda=1.5 and transistor width of 4Twrite circuitry has width 480nm and all other transistor width 120nm. I am attaching the schematic and circuit diagram. Please help me . why power is too high. 

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  • Dear Aswathan,

    Aswathyn said:
    Please help me . why power is too high. 

    I know very little about MTJ devices. However, I did make one observation - which may be totally incorrect as I cannot read your schematic well.

    In all honesty, for me, there really is not enough information about your simulation, schematic, and model to provide an answer with any degree of accuracy. For example, I can barely read your schematic and there do not appear to be any node names. As a result, the only observation I can make is that the two MTJ devices do not appear to have a write control signal connected to them. Both nodes are connected to ground through a resistor and hence I do not understand how this can implement a NAND?AND gate as there is no signal to cause the MTT devices to switch state. The conceptual diagram, which I think you probably copied from images, clearly shows a write signal connected to the control pins of each MTT model.

    Sorry I can not be of more help...

    Shawn

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  • Dear Aswathan,

    Aswathyn said:
    Please help me . why power is too high. 

    I know very little about MTJ devices. However, I did make one observation - which may be totally incorrect as I cannot read your schematic well.

    In all honesty, for me, there really is not enough information about your simulation, schematic, and model to provide an answer with any degree of accuracy. For example, I can barely read your schematic and there do not appear to be any node names. As a result, the only observation I can make is that the two MTJ devices do not appear to have a write control signal connected to them. Both nodes are connected to ground through a resistor and hence I do not understand how this can implement a NAND?AND gate as there is no signal to cause the MTT devices to switch state. The conceptual diagram, which I think you probably copied from images, clearly shows a write signal connected to the control pins of each MTT model.

    Sorry I can not be of more help...

    Shawn

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