Power and delay of digital circuits using cadence

Good Sir,

1. I'm not an expert in DPTL-C2MOS, but I'm sure that the static power dissipation depends on the input combination. For NAND/AND it is easy to simulate all input pairs. Maybe then you could pick the worst one as your static power.

2. You can add 'saveOptions options pwr=all' to the end of your spectre inputfile or if you use  ADE: Outputs->Save all ->Select power signals to ouput(pwr) and check 'all'.

You find the power graphs in Viva in Windows->Assistants->Browser and plot them and import them in the calculator and compute the average and so on ..

Kind Regards,

Iqbal

Dear Aswathyn,

I've taken a stab at providing some thoughts on each of your questions below. Your second question is related to your third and hence information regarding my response to it is implicitly included.

Aswathyn said:

If I make A,B and clock to 1V Vdc, it gives another power. so do I add both or which is actual static power?

Aswathyn said:

3. how can we choose clock frequency and pulse period of A and B for delay calculation. Is there any rule to set that pulse period and run time of simulation etc.

I've placed a note with my comments and simulation examples at URL:

https://www.dropbox.com/s/jvihxil18xl6sh1/static_power_tpd_meas_comb_sequential_logic_082822v1p0.pdf?dl=0

I hope this provides some thoughts on what paths you might consider for both your static power estimate and determining relevant and accurate propagation delay times.

Shawn

Sir, while calculating power suppose if i give input A and B 0V, then what about the clock is it set to IV(enabled) or 0v

Dear Aswathyn,

Aswathyn said:

while calculating power suppose if i give input A and B 0V, then what about the clock is it set to IV(enabled) or 0v

As with all the other combinatorial inputs to your circuit, the static power needs to be computed with the clock in each valid state. This is especially important in clocked logic as when the clock is in one state, some of the nodes can assume a high-impedance state. If you are not using "keeper" devices to hold the state of dynamic nodes, their voltages will vary with time and a transient simulation to estimate static power is advised.

I hope I understood your question Aswathyn and this helps you a bit!

Shawn

thankyou sir for your reply. one more doubt

while calculating delay in the case of nand gates we need to consider either A or B and the out for calculation or both  A and B with respect to out.