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Post Layout Netlist - does order of devices and parasitic caps matter for accurate results?

firebolt

Av_extracted post layout netlist has instance & devices definitions at the top. Parasitic caps at the bottom within subckt ends. My question is does order of parasitic caps in polo netlist matter for simulations? Because I am seeing different results with different combinations. I have 3 test cases.

1. original netlist with devices at top & caps at bottom -> jitter=10%

2. netlist with devices at bottom & caps at top -> jitter=18%

3. netlist with devices at top & sorted caps at bottom -> jitter=15%

4. netlist with devices at bottom & sorted caps at top -> jitter=12%

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  • This should not be the case. The order can influence how the matrix is constructed, but it should converge to a result within tolerances regardless. The only situation where you would get a significantly different result is when the circuit has multiple stable operating points - which is generally an indication of a circuit problem (of course, the circuit may intentionally have multiple stable operating points, such as with memory structures, flip-flops etc). The variation in results you are seeing is surprising, but of course it might be that the jitter is very small or that you're using transient noise and the random variation accounts for the difference - I don't know enough about how you're simulating to know the answer. However, you really should not be getting significantly different results purely based on the netlist order.

    I would suggest you contact customer support.

    Andrew

  • in reply to Andrew Beckett

    Thanks Andrew. This is transient simulation. I am injecting pwl noise to vdd and measuring deterministic jitter of final output clock. Yes, all 4 test case jitter numbers are close (above numbers are just relative, not actual ones) but original netlist is passing spec. Other cases are slightly exceeding spec. Even on reruns, I get the same results. That's why I was curious how the algorithm works.

    Thanks for reply. Slight smile

Reply
  • in reply to Andrew Beckett

    Thanks Andrew. This is transient simulation. I am injecting pwl noise to vdd and measuring deterministic jitter of final output clock. Yes, all 4 test case jitter numbers are close (above numbers are just relative, not actual ones) but original netlist is passing spec. Other cases are slightly exceeding spec. Even on reruns, I get the same results. That's why I was curious how the algorithm works.

    Thanks for reply. Slight smile

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