• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. Override a VerilogA parameters module while in tran Analysis...

Stats

  • Locked Locked
  • Replies 0
  • Subscribers 125
  • Views 7149
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Override a VerilogA parameters module while in tran Analysis.

Omar Ghazal
Omar Ghazal over 2 years ago

Hi Everyone

I Want to change 3 parameters in-sided a Verilog A module while in tran Analysis this change is triggered by the cross event every time  the voltage across 0V.

my parameter's new values are stored in a parameters file that produces in Matlab.
how to connect this file with the transition analysis so whenever a crossing the 0V new values update to the parameters from the next index.

here is the event

@(cross(V(P,N) - 0, +1))
begin
x=xnew;
y=ynew;
z=znew;
index=index+1;
end

here is a sample of the data file

Thanks 

  • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information