Crosstalk Simulation Setup

Dear ErickelRojo,

ErickelRojo said:

I'm currently trying to simulate a circuit including two different clocks running at two different frequencies. Both clocks are subsequently divided throughout the circuit and at the outputs of interest I am concerned on the clock quality degradation (from harmonics/spur perspective) due to the parallel clock running at the same time. Due to the active blocks included along the clock chains, I am interested to know how the source clock harmonics couple/fold down to the divided clocks of interest at the outputs.

ErickelRojo said:

My output of interest is at one of the divider's output (f1 = source1 / 2), while the other divider is running at the same time (f2 = source2 / 2)

Thank you for the explanation of both your problem and your objective! I believe both are clear to me. As you have noted, the use of a PSS or QPSS solution would save a significant amount of simulation time. However, in the general case that you are describing, the ability to find a steady-state solution is not realistic. It may be possible to choose a specific set of frequencies and phases for f1 and f2 to allow a steady-state solution with a reasonable period to exist (and hence utilize a PSS simulation), but this response will not be accurate for arbitrary frequencies and phases of f1 and f2.

However, some insight into the crosstalk may be gained without performing numerous transient analyses. If I may, let me pass a few thoughts by you if you have the time and patience ErickelRojo.

Determining a metric for your crosstalk

One item that was not clear to me as I read your description is your perception of "clock quality degradation". What is/are your measure(s) of "clock quality degradation"? I might suggest that time interval error of the victim clock might be a reasonable metric. This metric will the impact of crosstalk noise that results in significantly impacting transition times, runt pulses that cross clock buffer/divider thresholds, missing clock pulses, and supply noise. In addition, the nature of the TIE can be very helpful in determining the dominant crosstalk contribution means.

Simulating Crosstalk Effects using Time Interval Error as a Metric

Assuming your active networks do not contain resonator based VCO, and the frequencies f1 and f2 have periods that are far greater than the propagation delay of your active amplifiers and buffers/inverters, then you may be able to significantly reduce the number of simulations required to assess the impact of crosstalk. Specifically, in lieu of allowing the frequency of sources f1 and f2 to vary independently in frequency, I might suggest you set the frequency of both f1 and f2 to a common frequency, say fo, but allow their phases to vary over a full period. Measure the TIE of the victim clock as a function of the relative input phase.

In effect, this provides a view of how the impact of crosstalk varies as the two sources cross in phase. Of course, this could be accomplished by setting the two sources f1 and f2 to two different frequencies and examining the response over their beat frequency. However, this could be a very long simulation if the frequency of f1 and f2 are close! Stepping the phase manually with a common frequency for f1 and f2 does not require you to locate the exact time when the two sources phase cross at a specific node in your netlist.

If your main concern is not amplitude distortion of the victim clock, I believe this also captures the effect of crosstalk produced by the harmonics of two different frequency sources as those harmonics will appear as disturbances at some phase between your two sources as a phase sweep will include that phase.

Other Means to Assess Crosstalk

A second method I have used is to study the internodal capacitance of your presumably extracted view based netlist. This is most efficiently performed using a capacitance only based extracted view to create netlist in combination with Virtuoso's schematic editor.

Finally, as you likely are very aware, if your netlist contains primarily logic gates, there are digital STA tools that can be use to analyze crosstalk. The results of this type of analysis can provide some information - albeit not to the extent you will require!

I hope this helps ErickelRojo...

Shawn