• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. Uncorrelated Noise for Ports

Stats

  • Locked Locked
  • Replies 2
  • Subscribers 124
  • Views 7111
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Uncorrelated Noise for Ports

illaoi
illaoi over 2 years ago

Hi,

I wanted to do phased array front-end simulation and needed Mutiple ports with uncorrelated noise, however in my tran noise sim, I see the difference between two nets are zero which means they have the same noise which is not the case in phased array systems. Any suggestion to address this issue?

Thanks

  • Cancel
Parents
  • Andrew Beckett
    Andrew Beckett over 2 years ago

    I didn't believe this, so I just tried it and don't see this behaviour (I can't really see how the noise of the two nodes - I assume you mean the top end of each resistor - can be the same). Are you sure you've actually enabled transient noise?

    What does your input.scs look like?

    Here's my test (a handwritten netlist, but should be similar):

    //

    port0 (n1 0) port
    r0 (n1 0) resistor r=50

    port1 (n2 0) port
    r1 (n2 0) resistor r=50

    tran tran stop=1u noisefmax=1G

    and here's the results - the top two traces are n1 and n2, and the bottom is the difference:

    Andrew

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • illaoi
    illaoi over 2 years ago in reply to Andrew Beckett

    Andrew,

    Thanks, here is input.scs, but you are right, I probably made a mistake on plotting, now it works as expected.

    R1 (net2 0) resistor r=50
    R0 (net1 0) resistor r=50
    PORT1 (net2 0) port r=50 type=sine freq=frf dbm=prf
    PORT0 (net1 0) port r=50 type=sine freq=frf dbm=prf isnoisy=yes
    simulatorOptions options psfversion="1.4.0" reltol=1e-3 vabstol=1e-6 \
    iabstol=1e-12 temp=27 tnom=27 homotopy=dptran scalem=1.0 scale=1.0 \
    gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 digits=5 cols=80 pivrel=1e-3 \
    sensfile="../psf/sens.output" checklimitdest=psf fixdanglingnodes=1 \
    fixtopologyresistor=1e10
    tran tran stop=160.08n errpreset=liberal noisefmax=30G noiseseed=1 \
    psdplotparams=[40p 160.04n 16 3 25G] write="spectre.ic" \
    writefinal="spectre.fc" annotate=status maxiters=5

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • illaoi
    illaoi over 2 years ago in reply to Andrew Beckett

    Andrew,

    Thanks, here is input.scs, but you are right, I probably made a mistake on plotting, now it works as expected.

    R1 (net2 0) resistor r=50
    R0 (net1 0) resistor r=50
    PORT1 (net2 0) port r=50 type=sine freq=frf dbm=prf
    PORT0 (net1 0) port r=50 type=sine freq=frf dbm=prf isnoisy=yes
    simulatorOptions options psfversion="1.4.0" reltol=1e-3 vabstol=1e-6 \
    iabstol=1e-12 temp=27 tnom=27 homotopy=dptran scalem=1.0 scale=1.0 \
    gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 digits=5 cols=80 pivrel=1e-3 \
    sensfile="../psf/sens.output" checklimitdest=psf fixdanglingnodes=1 \
    fixtopologyresistor=1e10
    tran tran stop=160.08n errpreset=liberal noisefmax=30G noiseseed=1 \
    psdplotparams=[40p 160.04n 16 3 25G] write="spectre.ic" \
    writefinal="spectre.fc" annotate=status maxiters=5

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information