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Extraction Result Issue

I have made a schematic and it's layout and extracted the layout. DRC and LVS results are fine. When I simulate only schematic view then the results are fine. But when I simulate results are not making any sense even AND gate is not working. For example, inputs of AND gate is both high but output looks like it stuck in meta stable state. Is there any issue with my extraction view? Can you please help me with this?

Andrew Beckett over 2 years ago

There's simply not enough information to go on here. I suggest you contact customer support, as seeing more detail as to what you are simulating, what the extraction looks like and so on will be important to debug this.

Andrew
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