Bus termination error?

Ahh, I misread it. It only sees a connection to status_i<13:0>  within the rest of the chip(not shown), and arbitrarily

i suppose it assigned vss! to status_i<319>.     So How do I assign vss! to status_i<319:14>?

you can use <*306>vss! for connecting 306 vss! to status_i<319:14>

Another warning message I'm afraid.   The control_o bus,by adding a noconn and assigning it width was perfectly happy.

LOL, the next layer of the onion was that the patch was not defined as multi bit in the standard manner. But I still get an error, this time bus width matching which I don't get.

With the connection expression being 0:305=0:305 then it produces no warnings (I set this up without looking at your various attempts along the way).

Andrew

Thanks Andrew, but why didn't my vectors work?

The reason it didn't work is because you have the wire connected to the left of the patch only having 306 members, and so you can't possibly extract 319 through to 14 - because it doesn't have 320 members!

I would, however, have expected it to have worked if the bus to the left of the patch cord was labeled <319:0> rather than <319:14> - then you're picking part of this bus. However, it seems to set the wrong portion of the bus to be aliased to vss!, which I can't explain.

I'll chat with the schematic extractor team about this tomorrow. There's been a major rework of the schematic extractor (a brand new implementation), but this behaviour exists in both older versions and the new extractor - I can't quite explain why it should be like this.

Andrew

I can explain this now. Having thought about it and discussed with colleagues in R&D, it makes sense, although I am proposing some improvements to the documentation to make it clearer.

The Connection Expression on the patchcord is not referring to an index into a bus, as such. but instead it's generating a range of indices into the expanded bus on each side. The reason for this is that this generalises properly when the signal on the src or dst side of the patch is a bundle - and that is also handled consistently.

If I give a little example; this is similar to one in the documentation, except I reversed the Connection Expression - in the original they were 0:7=0:7 and 8:15=0:7. As we'll see, it actually doesn't matter which order they are in as you get the same result in both cases:

What's happening is that the bus on the left is expanded to:

"SYSBUS<15>" "SYSBUS<14>" "SYSBUS<13>" "SYSBUS<12>" "SYSBUS<11>"
"SYSBUS<10>" "SYSBUS<9>" "SYSBUS<8>" "SYSBUS<7>" "SYSBUS<6>"
"SYSBUS<5>" "SYSBUS<4>" "SYSBUS<3>" "SYSBUS<2>" "SYSBUS<1>"
"SYSBUS<0>"

and the buses on the right are expanded to:

"DATA<7>" "DATA<6>" "DATA<5>" "DATA<4>" "DATA<3>"
"DATA<2>" "DATA<1>" "DATA<0>"

and

"ADDR<7>" "ADDR<6>" "ADDR<5>" "ADDR<4>" "ADDR<3>"
"ADDR<2>" "ADDR<1>" "ADDR<0>"

in other words, a left to right expansion. All as expected. The Connection Expression is giving indices into this expanded list. So an expression of:

7:0=7:0

is stating that bit 7 maps to bit 7, bit 6 maps to bit 6 and so on. That's exactly what 0:7=0:7 does too. Now, bit 0 is the first element in the expanded bit on each side, so this means that this mapping occurs:

("SYSBUS<15>" "DATA<7>")
("SYSBUS<14>" "DATA<6>")
("SYSBUS<13>" "DATA<5>")
("SYSBUS<12>" "DATA<4>")
("SYSBUS<11>" "DATA<3>")
("SYSBUS<10>" "DATA<2>")
("SYSBUS<9>" "DATA<1>")
("SYSBUS<8>" "DATA<0>")
("SYSBUS<7>" "ADDR<7>")
("SYSBUS<6>" "ADDR<6>")
("SYSBUS<5>" "ADDR<5>")
("SYSBUS<4>" "ADDR<4>")
("SYSBUS<3>" "ADDR<3>")
("SYSBUS<2>" "ADDR<2>")
("SYSBUS<1>" "ADDR<1>")
("SYSBUS<0>" "ADDR<0>")

In my picture above, it would also have worked with the bus to the left of the patch being labelled status_i<319:0> (rather than <319:14>) provided that the Connection Expression remained as 305:0=305:0 as it means that the first 306 bits of status_i<319:0> are mapped to vss! and the rest are left alone - i.e. status_i<13:0>. Equally it works with the bus labelled as I did it.

The only case when the order matters with the Connection Expression is if you flip the order between the two sides, for example 7:0=0:7 because that means bit 7 maps to bit 0, bit 6 maps to bit 1 and so on.

Hopefully that's clearer! It's all logical once you think about it - it's easiest to think in terms of patch cords mapping between bits of expanded buses/bundles and then it all makes sense.

Regards,

Andrew