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portorder not being ignored?

kenc184

For my next trick.......

I'm creating a design top level symbol to be embedded in the pad ring schematic.

First: there are three global pins at this level, two of them vbat! and vss! are inputs to the design. One, vplus! is an I/O created by a regulator.

All three appear in the pin list in a "create cellview from cellview"  shown in pic one left pins RHS and top pins LHS.

When I create the symbol, it creates none of the global pins on the symbol as expected, BUT complains that vss! is not present in the symbol portorder despite me setting options as per the Cadence app note so that portorder errors/warnings are not generated.

I checked an old schematic/symbol pair and regenerated its symbol. Hey presto, a portorder warning. This did not happen before, I wonder if it's a version bug, I did update recently.

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  • kenc184

    Any ideas why the usual "trick" for ignoring portorder isn't working?  

  • Andrew Beckett
    in reply to kenc184

    Are the pins really global or are they pins with net expressions (i.e. inherited connections)? It's very unusual to have pins which are global. 

    Anyway, my attempts to reproduce this failed - I think there's too many unknowns to guess, so you should contact customer support so that an application engineer can take a look at the data and precisely what you're doing.

    Andrew

  • kenc184
    in reply to Andrew Beckett

    I've contacted support, regarding my other forum post on VEC, the system rejected my reply as Spam. I've appealed, so we'll see.

  • kenc184
    in reply to Andrew Beckett

    A CCR was created and after a couple of months, this is the response.

    I think they just repeated the problem rather than supplying a solution, but it's as clear as mud to me....

    Yesterday R&D updated us on the CCR as 

    "vicCheckPinOrder" flag only prevents the cross-view check from comparing portOrder properties between views. (symbol vs schematic etc.)

    In the testcase, a terminal in the symbol is missing from its portOrder property listing. There is no way to turn this check off. We think it necessary to report on stale data in the portOrder property.

    It is best that the portOrder proerty is not used in flows that donot need it.
    For this purpose, deleting the portOrder property is the way forward.Regenrating symbol wont hehlp bBecause a regeneration of the symbol by "Create CellView from CellView" reinstates the portOrder property.


  • Andrew Beckett
    in reply to kenc184

    Do you have the CCR number? Or Case number? I can take a look.

    The portOrder property is pretty unimportant in practice - the only thing that really needs it is for Verilog netlisting of leaf cells where implicit netlisting is used; other netlisters do not use it. It doesn't really matter about consistency - most of the checks are there for legacy behaviour.

    Andrew

  • kenc184
    in reply to Andrew Beckett

    Andrew: Yes, I just want to turn the warning OFF, but it won't let me. Hence the CCR 2735211 

  • kenc184
    in reply to Andrew Beckett

    Did you get a chance to look at the case Andrew?

  • kenc184
    in reply to Andrew Beckett

    Still would appreciate you looking at this Andrew. Noo idea if these replies are getting to you.

    I now have several blocks in my design which do not respond to disabling the portorder check via the cross-view "check pin order".

    Case number is 46659590.

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  • kenc184
    in reply to Andrew Beckett

    Still would appreciate you looking at this Andrew. Noo idea if these replies are getting to you.

    I now have several blocks in my design which do not respond to disabling the portorder check via the cross-view "check pin order".

    Case number is 46659590.

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