How to make sure Pnoise is giving correct results?

Dear HnArd,

HnArd said:

I have 6 stages of inverters, single-ended, with routing and backannotation in my schematic. 

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HnArd said:

What doesn't make sense to me is that Jee of stage 3 was reduced from stage 2 and the same happened to stages 4 and 5.

There are multiple reason that your simulated values of Jee for each stage may not monotonically increase and/or follow the typical behavior for random noise.

1. The Cadence definition of Jee relies on the slope of the waveform. Hence, if the load capacitance of each of your inverter stages is  not identical, then the Jee will show some variation from the anticipated monotonic behavior. You noted that you are using "backannotation" and hence I do not know how well matched each inverter's load differ.

2. The overall load capacitance average can impact the relationship between random noise and stage number. Please see Figure 1 from reference [1] for an example with a light load (3f) and heavier load per inverter (18f).

3. The accuracy of your simulation and the type of simulator can lead to a variance in Jee. Using a more accurateThe natural variance in Jee may cause the change in Jee per stage to deviate from your expected behavior. Increasing simulator accuracy settings or using a more accurate simulator can help to eliminate this as a potential source of variation.

4. Finally, if your "backannotation" includes supply impedance, then the noise profile seen in your supply current will appear on the supply and result in power supply noise. It is a well established fact (see reference [2]) that supply noise can be enhanced or reduced at an inverter output depending on the propagation delay of the inverter and the noise frequency. It can also result in even stage/odd stage variation in output noise - which appears to be what you are observing. Your odd stages show less Jee than your even stages.

I thought I should pass these along to you for possible consideration HnArd,

Shawn

Figure 1, from page 6 of Jenkins, K. A. "Jitter and timing measurement with CMOS circuits", IBM T.J. Watson Research Center

[2]. M. S. Illikkal, J. N. Tripathi, V. K. Sharma, H. Shrimali and R. Achar, "Novel Observations and Physical Insights on PSIJ Behavior in CMOS Chain-of-Inverters," in IEEE Access, vol. 10, pp. 100172-100177, 2022, doi: 10.1109/ACCESS.2022.3206019.

Thank you very much ShawnLogan for your reply. 

ShawnLogan said:

1. The Cadence definition of Jee relies on the slope of the waveform. Hence, if the load capacitance of each of your inverter stages is  not identical, then the Jee will show some variation from the anticipated monotonic behavior. You noted that you are using "backannotation" and hence I do not know how well matched each inverter's load differ.

Surprisingly, the slew rate of stage 5 is better than stage 6 but the slew rate of stage 4 is worse than stage 3.

ShawnLogan said:

2. The overall load capacitance average can impact the relationship between random noise and stage number. Please see Figure 1 from reference [1] for an example with a light load (3f) and heavier load per inverter (18f).

Yes, that is correct. But the total jitter is still increasing as we get closer to the load.

ShawnLogan said:

3. The accuracy of your simulation and the type of simulator can lead to a variance in Jee. Using a more accurateThe natural variance in Jee may cause the change in Jee per stage to deviate from your expected behavior. Increasing simulator accuracy settings or using a more accurate simulator can help to eliminate this as a potential source of variation.

I have changed the accuracy and I am now using the highest precision for my simulation. No big change was observed.

ShawnLogan said:

4. Finally, if your "backannotation" includes supply impedance, then the noise profile seen in your supply current will appear on the supply and result in power supply noise. It is a well established fact (see reference [2]) that supply noise can be enhanced or reduced at an inverter output depending on the propagation delay of the inverter and the noise frequency. It can also result in even stage/odd stage variation in output noise - which appears to be what you are observing. Your odd stages show less Jee than your even stages.

No, I didn't include supply impedance in my simulations. I am using an ideal supply/ground in my simulations. 

Dear HnArd,

First, thank you for your careful reading of my comments - and for adding your additional information and experimental results! The additional information is very helpful to me.

HnArd said:
Yes, that is correct. But the total jitter is still increasing as we get closer to the load.
Looking at your data, the overall trend is also increasing with stage number.

HnArd said:
Surprisingly, the slew rate of stage 5 is better than stage 6 but the slew rate of stage 4 is worse than stage 3.
This may make sense. The output noise of a given inverter is dependent not on the slope of its output waveform, but the slope of its input waveform as shown in the following note.inverter_chain_112622.pdf

Hence, if the slew rate of your inverter 4 is slow (i.e. input to inverter 5), the output of inverter 5 will show an increase in jitter as its input waveform remains about the switching threshold for a long period of time. The slew rate of inverter 6 almost does not matter as your jitter measurement is made at one specific voltage - it is an ideal sampler.

HnArd said:
I have changed the accuracy and I am now using the highest precision for my simulation. No big change was observed.
Great!

HnArd said:
No, I didn't include supply impedance in my simulations. I am using an ideal supply/ground in my simulations.
This is good information too. Hence, the impact of supply noise is not present in your simulation results.

I hope this helps unravel the issue a bit more HnArd...

Shawn