Monte Carlo Mismatch Operating Region Discrepancy

Dear illaoi,

illaoi said:

For a given NFET, on left plot I am showing VGD (DC) in red and Vth in Yellow, both from op in calculator.

If it is an NFET, I am wondering why are you measuring VGD to compare with the threshold voltage in lieu of VGS?

illaoi said:

On the right plot, I am showing "region" from op, which shows this FET swaps between triode and sat across monte-carlo, though why I see that VGD>Vth for all cases which means I should get triode in all cases and region of 1.

The conditions for an NFET to be in its linear (or triode region) and its saturation region are two-fold:

Linear Region:

1. VGS ≥ Vth
2. VDS < VGS – Vth

Saturation Region:

1. VGS ≥ Vth
2. VDS > VGS – Vth

Have you considered examining these two conditions to determine the region?

1. VGS - Vth : Is this difference greater than zero?

2. VGS - VDS: Is this difference greater or less than Vth

Shawn

Shawn,

You are saying check if your FET is in sub-threshold or not, however if it was in sub-threshold, the op region should have provided region "3". Isn't that, right?

Dear illaoi,

illaoi said:

You are saying check if your FET is in sub-threshold or not, however if it was in sub-threshold, the op region should have provided region "3". Isn't that, right?

I guess my response was not clear - sorry illaoi! What I am suggesting is that you are not looking at the proper MOS terminals for an NMOS device to determine its operating region. For an NMOS device, if the VGS exceeds the threshold voltage, it is defined as being in Region 1 if VDS < VGS – Vth, and in region 2 if VDS > VGS – Vth.

In the plot you provided in your initial Forum post, you commented: 

illaoi said:

I am showing VGD (DC) in red and Vth in Yellow, both from op in calculator

However, for an N-chanel device, you should be comparing VGS (not VGD) to the threshold voltage and VDS to the difference between VGS and Vth to establish the operating region.

I hope this clarifies my comments illaoi.

Shawn

Shawn,

I do not know your level of expertise in CMOS, but this that you shared VDS < VGS – Vth is mathematically equivalent to VGD>Vth and this VDS > VGS – Vth is mathematically equivalent to VGD<Vth.

Therefore, if the transistor is not in sub-threshold, or does not have VGS>Vth, comparing VGD to Vth should specify if it is in region 1 or 2, and I suppose you guys define region 3 for when VGS<Vth. Also, this is independent of FET being N or P type!

Dear illaoi,

illaoi said:

I do not know your level of expertise in CMOS, but this that you shared VDS < VGS – Vth is mathematically equivalent to VGD>Vth and this VDS > VGS – Vth is mathematically equivalent to VGD<Vth.

You are correct as I show in the following drawing.

illaoi said:

Therefore, if the transistor is not in sub-threshold, or does not have VGS>Vth, comparing VGD to Vth should specify if it is in region 1 or 2,

Your comment "or does not have VGS > Vth", is not quite accurate as region 1 and region 2 both require VGS >= Vth.

As I mentioned in my first response, there are two distinct conditions on the device terminals (assuming the bulk node is connected to the substrate and it is grounded) to determine if an NMOS device is in its linear or saturated region. In your initial post, you only show VGD and compare it to Vth. In my drawings below, this is condition 2. However, maybe it is obvious to you, but from what I read in your post, you did not indicate the value of VGS relative to the threshold voltage. Without knowledge of VGS relative to Vth, I'm not sure how you expect to determine the device operating region. Do you agree illaoi?

illaoi said:

and I suppose you guys define region 3 for when VGS<Vth. Also, this is independent of FET being N or P type!

I'm not sure what you mean by "you guys". I am a designer just trying to help out where I think I can.

Shawn

Shawn,

You are correct and I said it in two messages ago that you were asking if the FET is in subthreshold, my point was, isn't the subthreshold region 3?

That means although I have not shown VGS compared to Vth, from the regions plot, it is obvious that it never goes to region 3 which means VGS>Vth.

Dear illaoi,

I am sorry to frustrate you and apologize. I guess I can not be of any help.

Shawn

Dear Shawn and illaoi,

as far as i know, the simple "square-law"equations for the regions do not apply for BSIM3, BSIM4 (and their derivatives) that you are using in your simulation.

The model covers 5 different regions:

- off (region=0), when VGS<Vth-10*VT
- sub-threshold (region=3), when Vth-10*VT<=VGS<Vth
- saturation (region=2), when VGS>=Vth & VDS>vdsat
- ohmic (region=1), when VGS>=Vth & VDS<=vdsat
- breakdown (region=4)

In the above shown equations, VT equals to the thermal voltage, and vdsat is equal to the saturation voltage.You can probe vdsat as operating point (similar to the region).

It is important to notice that vdsat is NOT equal to VGS-Vth, as in your equations.
AFAIK, vdsat=(VGS-Vth)/M, with M>1, so as a result the boundary between saturation and ohmic is at lower values of VDS than the square-law predicts.

You can look up this behavior in the Spectre Circuit Simulator Components and
Device Models Reference (spectremod.pdf). There you can find for the model BSIM4 Level-14 Model (bsim4) in the subsection Device Regions a nice chart which explains the regions of the device.

@illaoi, I suggest that you cross check the region from simulation with the inequations above, hopefully that solves your problem.

Kind regards
Matthias

A small update: You can find the derivation for vdsat in the book Physics of Semiconductor Devices (Simon M. Sz, Kwok K. Ng) in 6.2.2 (Current-Voltage-Characteristics).

Matthias,

Very thorough explanation, appreciate it.