Differential .stb analysis by referencing terminals on an av_extracted view including devices with multiplier

Dear davidl,

DavidI said:

So in short: I fail to do on terminal based .stb on an av_extracted view including devices with multipliers

This situation is very common in my everyday life and I hopped to get a proper .stb without schematic manipulation (e.g. with the rmetal plus deepprobe approach)

Does anyone know a solution?

Maybe you have tried this, but one way to work around this particular issue is to add a metal resistor in your layout that is in series with your four parallel P and N input devices. You also add this metal resistor to your schematic. Hence, using a terminal of this added metal resistor in your stability analysis assures all four devices comprising your P and N differential pair are included in the analysis. A recent article discusses this in  greater detail. I was not sure if you saw this and were able to try it.

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000tt0rEAA&pageName=ArticleContent

Shawn

Hey Shawn,

thanks for your answer. Yes I am aware of this approach. So I see three methods to do the a differential .stb in general:

1)  break the loop in the schematic, add pins, route the feedback nets up to block top level and close the loop with a diffstbprobe on test bench level

2) use metal resistor which can break the loop via blanking out in the config view and use deepprobes to connect the nodes

3) use the .stb approach with terminals

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1) and 2) can lead to  messy block top level and test bench in a complex system with multiple feedback loops (and It also creates unnecessary overhead for layout)

3) looks like a perfect solution to overcome all the manipulation needed for 1) and 2)

Unfortunatly 3) is failing for av_extracted in  this case I described. Though It works perfectly for schematic views.

I really would like to move to method 3)  in the future for my full stb verificaton flow but currently I always have do either 1) or 2) to cover av_extracted verificaiton.

regards

David

Update: I should emphasize that I am focusing on differential stability analysis. For single ended ended system I use a negligible metal resistor in series with the gate of the input transistor of the error amplifier. Then I use the terminal of this metal resistor in the .stb analysis. This method is working perfectly for schematic and av_extracted views. The difference to differential problems is that differential .stb must use the terminal of a leaf device. And a metal resistor is not a leaf device. Hence differential is not working with the metal resistor. I always have to probe the gate of the input transistor.

Dear Davidl.

Thank you for your added details and very clear description of your issue!

DavidI said:

For single ended ended system I use a negligible metal resistor in series with the gate of the input transistor of the error amplifier. Then I use the terminal of this metal resistor in the .stb analysis. This method is working perfectly for schematic and av_extracted views.

Great!

DavidI said:

The difference to differential problems is that differential .stb must use the terminal of a leaf device. And a metal resistor is not a leaf device. Hence differential is not working with the metal resistor. I always have to probe the gate of the input transistor.

Let me apologize up front if I am misunderstanding your comment...but it seems that if you add a metal resistor, rm_p in series with the gates of the 4 P rail devices (at some common net in the layout) and a second metal resistor, rm_n in series with the gates of the 4 N rail devices as shown below, you could enter the two resistor terminals shown as the terminals in the differential stb analysis. Does your comment suggest this does not work?

Shawn

Shawn,

Thanks for this. As the author of the article you reference which has existed for many years now, I had updated it recently to reflect the newer use model of being able to specify the terminals that you wish to insert (in effect) the differential probe points at rather than having to use deepprobes to connect up to the top level and then use a config to "bind to open" the metal resistors. That approach is kept in the article for completeness, but the best way now is simply to do as you've suggested - place metal resistors in the schematic and layout, and then use the terminals of those metal resistors as the probe points. This avoids any need to disturb the hierarchy, no additional pins are needed, nothing special in the test bench - it's pretty straightforward.

I will tidy up the article just to clarify that this is the preferred approach (we fixed the use model issues with the new UI a few ISRs ago).

Regards,

Andrew

Dear Andrew,

Thank you, very much, for adding your insight and comments!! The background information regarding your article is very helpful.

Let's hope Davidl can try this and perform his differential stability analysis successfully.

Shawn

PS  I've always tried to avoid the use of deepprobes. The technique I've resorted to is to create a new schematic symbol for a probe that is actually a metal stub. I place the metal stub in the layout at exactly the location I want it and the symbol with a unique name at the probe point in the schematic. Hence, the mapping between schematic and extracted view netlists is identical which allows easy access to the extracted view net.

Hey Shawn,

thanks for the sketch, that reflects the situation well.

Exactly, my comment suggests that the method is not working. 

The .stb analysis window would e.g. look like this:

If you run, spectre will throw an error:

Error found by spectre during initial setup.
ERROR (SFE-2963): Cannot run the simulation because the leaf instance 'DUT.RM_N' could not be found. Specify a valid leaf instance terminal name for the stb analysis and rerun the simulation.
ERROR (SFE-2963): Cannot run the simulation because the leaf instance 'DUT.RM_P' could not be found. Specify a valid leaf instance terminal name for the stb analysis and rerun the simulation.

This is the point where I am stuck. If I use the metal resistor terminals, spectre throws an error as the resistor is not a leaf device as current can go both directions. Using one of the gates (which would fulfill the leaf devices requirement) gives incorrect results as only one 1/4 of the PMOS is taken into account.

Question for me are:

Is this a limitation of the .stb analysis?

Or do I miss something?

Andrew Beckett said:

This avoids any need to disturb the hierarchy, no additional pins are needed, nothing special in the test bench - it's pretty straightforward.

This is exactly the situation I would like to have

regards

David

Hi David,

It's probably best to do this by creating a case (service request) via customer support. This is absolutely not a limitation of the stability analysis; I'm wondering whether the metal resistors actually end up in the post-layout netlist? Can you check if the RM_N and RM_P instances are present in the netlist - and if so, can you share the instance lines from the input.scs/netlist?

Also, can you share what the stb analysis statement in the input.scs looks like?

Thanks,

Andrew 

Perhaps metal resistors are modeled with (inline) subcircuits in this technology. What is the technical reason for the limitation to terminals of leaf devices, anyway?

Frank Wiedmann said:

What is the technical reason for the limitation to terminals of leaf devices, anyway?

The simulator deals with the flattened design, and doesn't really insert a diffstbprobe or iprobe into the hierarchical design.

I'm not sure inline subckts would cause a problem (I've not checked though).

Andrew

Andrew Beckett said:

The simulator deals with the flattened design, and doesn't really insert a diffstbprobe or iprobe into the hierarchical design.

I'm just wondering why specifying a subcircuit terminal as the probe location apparently is a problem for the differential stb analysis, but not for the single-ended one (according to https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000tt0rEAA).