Difference between Transient and Transient+Noise simulation

Dear Senan,

Thank you for your information - it was most informative and provides some good clues as to a possible hypothesis as to the origin of your noise! I've responded to your answers and follow with a couple of items to consider if you have the time and patience!

Senan said:

1. I am using the 50 Ohm probe for measuring the supply noise, and for our chip circuit we used the 1 M ohms because our circuit, in particular, the amplifier prototype is not designed to drive a heavy load like 50 Ohm.

Excellent. The use a 50 ohm probe for measuring the supply is your best choice.

Senan said:

2.3.  We distributed several bypass capacitors at the time of our chip design, but you know the range can not be more than tens of pico farad due to the die size constraint.

This is very good information Senan. You are correct that the amount of internal bypass is limited by area constraints. However, it is essential to both include it in your layout and simulations as I think you will also conclude after my next set of comments.

Senan said:

4. Yes we connected bypass capacitors on our PCB board near to the supply, ground pins. We used a combination of 10 µF Electrolytic capacitor time plus 100 nF Ceramic type capacitor.

The 100 nF ceramics should help - but only up their self-resonant frequency. Depending on the physical size of your chip capacitor, their internal self-inductance will limit their use as a bypass element. For a 100 nF (0.10 uF), this is an example of their limited bypass frequency range of abut 20 MHz:

reference: Parasitic Inductance of Multilayer Ceramic Capacitors Jeffrey Cain, Ph.D. AVX Corporation

Senan said:

5. We are measuring the noise like measurement configuration number 1

Excellent!

Senan said:

6. Our package type is PGA 100 (Ceramic Pin Grid Array), one thing might be useful to mention, our chip area is small as compared to the package cavity but we used this type of package because we need 100 pins. As a consequence, the bonding wires are lonf to the maximum length allowed for packaging. 

Actually, the bonding wires was not considered by our simulation with its inductance, capacitance and resistance effect that also give an answer to the difference between out simulation in Cadence and the practical measurements we are observing. The highest level of simulation we performed is by including the pad frame. Even we are not aware if there is a simulation possibility that includes the package/bonding leads effect and could be interesting to know.

Unfortunately, the inductance of bond wires is quite significant and I think you might consider including its impact in your netlist and simulations. Both the mutual and self-inductances of a bondwire can impact high frequency performance. Intuitively, the presence of the bond wire acts as a filter with your on-chip capacitance. In the example I show below with a 50 pF internal bypass and a 5 nH wire bond inductance, the on-chip power impedance is inductive above 800 MHz - which is clearly not what your internal circuit was simulated with. Further, any amount of external bypass capacitance cannot reduce the impact of that wirebond inductance.

In addition, there is mutual coupling between adjacent bondwires, which may also lead to coupling between undesired nodes (such as an output node and a power node). The best you can do is to both model and attempt to minimize the impact of the bondwire inductance through internal bypass a package design.

You noted your chip is small relative to the cavity of the package in which it was placed. Is there any chance you can fit a small single layer ceramic capacitor (e.g. from Johanson) in the package and place multiple wirebonds to it and the chip VDD pads? In work I did many years ago, I was able to significantly reduce the impact of wirebond lead inductance using this methodology.

In trying to study your waveforms closely, it appears the frequency of your apparent oscillation is at about 6.5 MHz on both the supply, common-mode, and output waveforms. I am wondering if the presence of the package inductance is leading to a parasitic low level oscillation due to mutual coupling or the impedance of the internal supply coupled with your transient currents. If you expand the timescale, can you view any higher frequency oscillations superimposed over the 6.5 MHz?

You might also try varying the supply voltage and temperature/load to reduce the supply current to its lowest possible value to see if the amount or frequency of the apparent noise is changed.

A lot of words...but hope this helps provide an idea or two Senan.

Shawn

Dear Shawn,

I am very grateful for your help and the valuable comments you advised me to do, 

I would like to give you a feedback on it, first of all we were not allowd to put the internal capacitor in the chip like you suggested, rather we made new PCBs and located the capacitors near to the VDD, GND pins. We optimized the power routing as well with PCB ground plate. As a result the noise is largely reduced. 

However, the reality behind the large anplitude of the signal I shared before was in a noise, we dicovered that our amplifier was not too much stable and those are oscillating signals.

Back to the noise improvement, we have foundout new thing that might be another reason for noise contribution, during the design package, we did not connect the chip substrate to the package cavity. In some design I have explored, I found that  people are using epoxy conductive glue to attach the die to the package cavity then they routed to a ground pin or sometimes to the available extra pin of the package. So we have unfortunately missed this, and I would like to ask from your experience how big is important this step.

Thank you once again for your kind help and I wish you in advance a happy new year full of health and success.

Best Regards

Dear Senan,

First things first - thank you very much for your update!

Senan said:

irst of all we were not allowd to put the internal capacitor in the chip like you suggested, rather we made new PCBs and located the capacitors near to the VDD, GND pins. We optimized the power routing as well with PCB ground plate. As a result the noise is largely reduced. 

Excellent! I understand your constraints as fitting an internal bypass can be both a physical challenge and an expense. You were wise to explore other alternatives.Optimizing the power grid routing and using a ground plane are very good practices. In particular, the ground inductance provided by the ground plane should be much less than that provided by one or more traces to a pin.

Senan said:

However, the reality behind the large anplitude of the signal I shared before was in a noise, we dicovered that our amplifier was not too much stable and those are oscillating signals.

This also makes sense and was one of the items I commented on based on your waveforms and observations. Although perhaps not good news, at least you have identified it as a contributor - good work Senan!

Senan said:

Back to the noise improvement, we have foundout new thing that might be another reason for noise contribution, during the design package, we did not connect the chip substrate to the package cavity. In some design I have explored, I found that  people are using epoxy conductive glue to attach the die to the package cavity then they routed to a ground pin or sometimes to the available extra pin of the package. So we have unfortunately missed this, and I would like to ask from your experience how big is important this step.

It turns out, I do have some experience with the use of both conductive and non-conductive epoxies for chip attach. In the case I am referring to, there was a single sustaining amplifier placed in a ceramic package with a piece of quartz to form an oscillator that served as a timing reference. For some timing reference frequencies, I observed non-quartz related oscillations. I studied the use of a silver based conductive and non-conductive epoxies to secure the substrate of the silicon sustaining amplifier to the internal gold-plated ground plane. The internal ground plan connected to the package pins with additional gold plating - there were no wire bond connections from the internal ground plane to the package pins. If I recall (as it was some time ago), there was a slight difference in the frequency and magnitude of the parasitic oscillation, but the use of a conductive or non-conductive epoxy did not make a tremendous difference. However - the silicon device did have contacts from the substrate to its top level metal. Hence, the substrate was still electrically connected to ground through top level metal and its lossy vias. I do not know if your substrate is connected to top level metal. If it is not, then I think you should definitely consider using conductive epoxy and connect the surface to which the epoxy is connected to ground - even if it is with wire bonds.

A second item to consider, which I did not explore, was latch-up. The probability of latch-up is far greater and will be more pronounced on a device whose substrate is floating (as will its ESD robustness). Hence, in our case, we did choose to use conductive epoxy in lieu of a non-conductive epoxy for chip attach.

I hope my recollection provides some thoughts to consider Senan!

Shawn

Dear Sawn,

I am happy to tell you that with your nice help, our test with regard to the noise is largely improved

Thanks a lot for your patience and kind help

Best regards

Dear Senan,

Thank you for the update Senan! I am so happy to read you have been able to reduce your noise a bit - that is excellent work and I am sure took a lot of patience on your part Senan!  Good luck!

Shawn