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  3. N-to-1 mux control with selection being a variable

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N-to-1 mux control with selection being a variable

Karev11
Karev11 over 2 years ago

Hi,

I have six signals that needs to be mux'ed and it would be very beneficial if the mux control signal can be a variable (1, 1.5, 2, 3, 4, 1.5 is intended btw), so that I can use this value in my output definition directly.

Is there a way to do this ?

thanks,

Kevin

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  • Andrew Beckett
    Andrew Beckett over 2 years ago

    This sounds like a fairly simple Verilog-A model. If you look at the analog_mux model in ahdlLib, this uses an input called vsel to choose which of the two inputs are selected based on it being above or below the threshold. Rather than doing that, you could remove the vsel input and instead make the selector variable a parameter of the model - then that would select which voltage source is driving the output. The code doesn't have any transition handling, but if it's parameter-based, then that would be even less important. You could extend the condition to have multiple inputs - easy enough to write.

    However, I don't know what the control signal being 1.5 means - you'll need to expand on that.

    Andrew

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  • Karev11
    Karev11 over 2 years ago in reply to Andrew Beckett

    thanks Andrew, this idea works.

    in my case, mux sel is also clock divider ratio, if it's a numerical number, I can use it directly for output expression (frequency).

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  • Karev11
    Karev11 over 2 years ago in reply to Andrew Beckett

    thanks Andrew, this idea works.

    in my case, mux sel is also clock divider ratio, if it's a numerical number, I can use it directly for output expression (frequency).

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