N-to-1 mux control with selection being a variable

This sounds like a fairly simple Verilog-A model. If you look at the analog_mux model in ahdlLib, this uses an input called vsel to choose which of the two inputs are selected based on it being above or below the threshold. Rather than doing that, you could remove the vsel input and instead make the selector variable a parameter of the model - then that would select which voltage source is driving the output. The code doesn't have any transition handling, but if it's parameter-based, then that would be even less important. You could extend the condition to have multiple inputs - easy enough to write.

However, I don't know what the control signal being 1.5 means - you'll need to expand on that.

Andrew

Dear Kevin and Andrew,

Karev11 said:

I have six signals that needs to be mux'ed and it would be very beneficial if the mux control signal can be a variable (1, 1.5, 2, 3, 4,

Maybe I am overlooking something Kevin, but you noted you have six signals from which you desire to select one (or more, I am guessing). However, your note lists only 5 selector inputs. Is the selector value of 1.5 actually selecting more than one of your 6 inputs? In other words does the selector value of 1.5 choose, either periodically or directly connect, the 6th input signal combined with the selected value chosen by 1?

Andrew Beckett said:

This sounds like a fairly simple Verilog-A model. If you look at the analog_mux model in ahdlLib, this uses an input called vsel to choose which of the two inputs are selected based on it being above or below the threshold. Rather than doing that, you could remove the vsel input and instead make the selector variable a parameter of the model - then that would select which voltage source is driving the output.

If the selector input of 1.5 is somehow combining two of your inputs to its output, that might make Andrew's suggestion a bit more complex to implement. I did find an example of a veriloga 4 input analog multiplexer that appears to be capable of choosing more than one analog input to route to the output for a given selector input that appears below. However, its select input is a 2 bit bus and contains a decoder to set it internal variable SEL to the values of 0, 1, 2, or 3.  I'm not sure why the author defined module input sel as a 4 bit input.  It seems you could easily modify the decode to set SEL to the desired value to select between your 5  or 6 inputs for your selector values of 1, 1.5, 2, 3, and 4.

I am unable to verify this code - so I can't guarantee it will work (sorry!) - but thought I would pass it your way Kevin,

The code is from:

Shawn

module(out, in, sel);
output out; electrical out;
input [3:0] in; electrical [3:0] in;
input [3:0] sel; logic [3:0] sel;
parameter real vdd = 2.5;
integer SEL;
genvar i;

analog begin
    // convert the input to an integer
    SEL = 0;
    for (i = 0; i < 2; i = i + 1) begin
        @(cross(V(sel[i]) - vdd/2));
        if (V(sel[i]) > vdd/2)
            SEL = SEL + (1 << i);
        end

    V(out) <+ V(in[0])*transition(SEL == 0, 0, 100n);
    V(out) <+ V(in[1])*transition(SEL == 1, 0, 100n);
    V(out) <+ V(in[2])*transition(SEL == 2, 0, 100n);
    V(out) <+ V(in[3])*transition(SEL == 3, 0, 100n);
end
endmodule

Dear Kevin and Andrew,

Karev11 said:

I have six signals that needs to be mux'ed and it would be very beneficial if the mux control signal can be a variable (1, 1.5, 2, 3, 4,

Maybe I am overlooking something Kevin, but you noted you have six signals from which you desire to select one (or more, I am guessing). However, your note lists only 5 selector inputs. Is the selector value of 1.5 actually selecting more than one of your 6 inputs? In other words does the selector value of 1.5 choose, either periodically or directly connect, the 6th input signal combined with the selected value chosen by 1?

Andrew Beckett said:

This sounds like a fairly simple Verilog-A model. If you look at the analog_mux model in ahdlLib, this uses an input called vsel to choose which of the two inputs are selected based on it being above or below the threshold. Rather than doing that, you could remove the vsel input and instead make the selector variable a parameter of the model - then that would select which voltage source is driving the output.

If the selector input of 1.5 is somehow combining two of your inputs to its output, that might make Andrew's suggestion a bit more complex to implement. I did find an example of a veriloga 4 input analog multiplexer that appears to be capable of choosing more than one analog input to route to the output for a given selector input that appears below. However, its select input is a 2 bit bus and contains a decoder to set it internal variable SEL to the values of 0, 1, 2, or 3.  I'm not sure why the author defined module input sel as a 4 bit input.  It seems you could easily modify the decode to set SEL to the desired value to select between your 5  or 6 inputs for your selector values of 1, 1.5, 2, 3, and 4.

I am unable to verify this code - so I can't guarantee it will work (sorry!) - but thought I would pass it your way Kevin,

The code is from:

Shawn

module(out, in, sel);
output out; electrical out;
input [3:0] in; electrical [3:0] in;
input [3:0] sel; logic [3:0] sel;
parameter real vdd = 2.5;
integer SEL;
genvar i;

analog begin
    // convert the input to an integer
    SEL = 0;
    for (i = 0; i < 2; i = i + 1) begin
        @(cross(V(sel[i]) - vdd/2));
        if (V(sel[i]) > vdd/2)
            SEL = SEL + (1 << i);
        end

    V(out) <+ V(in[0])*transition(SEL == 0, 0, 100n);
    V(out) <+ V(in[1])*transition(SEL == 1, 0, 100n);
    V(out) <+ V(in[2])*transition(SEL == 2, 0, 100n);
    V(out) <+ V(in[3])*transition(SEL == 3, 0, 100n);
end
endmodule