Stats

  • Locked Locked
  • Replies 5
  • Subscribers 125
  • Views 8623
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Error in Spectre ADE simulation

ZaraF

Hi, 

I am working on the PSMC40nm pdk and the foundry has provided only hspice model files. I want to use spetre for simulation. So when I open ADE I switch the simulator to Spectre but I am still using the Hspice model files and I can simulate most of the circuits without any problems. When I check ADE/setup/environment the switch view list is: "spectre cmos_sch cmos.sch schematic veriloga ".

The problem is when I want to simulate a circuit containing some cells form 'rfTlineLib' library an I got this error in CIW window (ADE does not generate a log file): 

Unable to descend into any of the views defined in the view list, 'hspiceD spice cmos_sch cmos.sch schematic veriloga spiceText', for the instance 'stackup1' in cell 'channel_stack'. Add one of these views to the cell 'stackup' in the library 'rfTlineLib', or modify the view list so that it contains an existing view.

Do have any idea why this is happening?

Parents
  • Andrew Beckett

    First of all, if you're using a config view (not sure if you are), then that controls the view switching - you'd need to check that has the spectre view in the view list. Also check that ADE still has the right view list when you're using this component (I've no idea why it would have changed) - and finally check to see if you have a .simrc file in your environment (check working directory, home directory, and then <ICinstDir>/tools/dfII/local - could also check "cdswhich .simrc" at the UNIX prompt in case it's been set to be found via the CSF/setup.loc mechanism) - maybe that is overriding the switch list?

    Clearly the netlister thinks that the view list is the one containing hspiceD - the key here is to uncover why that is (it sounds a bit odd to me),

    Andrew

  • ZaraF
    in reply to Andrew Beckett

    Thanks for the reply. 

    1. I am not using the Config view. I am directly simulating a schematic view. 

    2. I am not sure how to check that ADE has the right view list. If you are referring to ADE/setup/environment the switch view list before running the simulation is: "spectre cmos_sch cmos.sch schematic veriloga ".

    3. When I run cdswhich .simrc, I get the following message:

     Info (cdswhich): '.simrc' found at: ./.simrc

    4. The .simrc file is available in my working directory and I have attached the file to this post.

    It looks like the view list is being overridden but it is not clear to me why and who is doing that. Any thoughts?

    The interesting thing is that I only get this error when I have a component in the schematic that does not have a Hspice view for example the "stackup" cell from " rfTlineLib". This is very weird as I am using spectre simulator (when I open ADE, the default simulator is Hspice and I switch it to Spectre before running simulations).

    Fullscreen simrc.txt Download 
    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;; Configulation for Verilog netlist
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
simVerilogNetlistExplicit = 't
hnlVerilogNetlistExplicit = 't
hnlVerilogNetlistBehavioralExplicit = 't
hnlVerilogNetlistNonStopCellExplicit = 't
;when(simSimulator=="verilog" hnlRegPostNetlistTrigger('SdVerilogPP))
; ---- for RTL Level verilog netlist extraction
verilogSimViewList = '("functional" "schVeri" "verilog70" "verilog" "schematic" "symbol")
verilogSimStopList = '("verilog70" "verilog" "functional" "symbol")

; ---- for Gate Level verilog netlist extraction
;verilogSimViewList = '("functional" "schVeri" "verilog70" "verilog" "schematic" "symbol")
;verilogSimStopList = '("verilog70" "verilog" "functional")


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;; Configulation for Spice netlist
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

simReNetlistAll = t
simVerilogDropPortRange = nil
simVerilogPwrNetList = '("VDD!" "VEXT!" "VEXTQ!")
simVerilogGndNetList = '("VSS!")
simVerilogSimTimeValue = 1
simVerilogSimTimeUnit = "ns"  
simVerilogSimPrecisionValue = 1
simVerilogSimPrecisionUnit = "ns"
simVerilogBusJustificationStr = "U"
simVerilogTestFixtureFlag = 'nil
simVerilogHandleSwitchRCData = 't
hnlVerilogIgnoreTerm = t

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;  Definition of Net Maping 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;hnlMapNetInName = list("*" '("+" nil) '("(" nil) '(")" nil) '("," nil) '("." nil) '("$" nil) '("[" nil) '("]" nil) '("!" nil))
;hnlMapNetInName = list("*" '("+" nil) '("(" nil) '(")" nil) '("," nil) '("." nil) '("$" nil) '("[" nil) '("]" nil) '("<" "_") '(">" nil) '("!" nil))

;hnlMapNetFirstChar = list("*"
;        '("+" "n")      '("(" "n")      '(")" "n")      '("," "n")      '("." "n")
;        '("$" "n")      '("[" "n")      '("]" "n")      
;        '("!" "n")
;        '("0" "n0")     '("1" "n1")     '("2" "n2")     '("3" "n3")     '("4" "n4")
;        '("5" "n5")     '("6" "n6")     '("7" "n7")     '("8" "n8")     '("9" "n9")
;        )
;hnlMapNetInName = list("*"
;        '("+" nil)      '("(" nil)      '(")" nil)      '("," nil)      '("." nil)
;        '("$" nil)      '("[" nil)      '("]" nil)      
;        '("!" nil)
;        )
;
;
;hnlMapInstFirstChar = list( "*"
;        '("+" "")       '("(" "")       '(")" "")       '("," "")       '("." "")
;        '("$" "")       '("[" "")       '("]" "")       '("_" "_")
;        '("!" "")       '("|" "|")
;        )
;
;hnlMapInstInName = list( "*"
;        '("+" nil)      '("(" nil)      '(")" nil)      '("," nil)      '("." nil)
;        '("$" nil)      '("[" nil)      '("]" nil)      
;        '("!" nil)
;        )


hnlMaxNameLength = 200
hnlMaxLineLength = 128

; The following three options added based on 2x 64GEX3 simrc
vlogExpandIteratedInst = t

vlogifVicSVTextCellViewList = (list "systemVerilogText" "text.v")
auCdlCDFPinCntrl=t
cdlSimViewList = '("auCdl" "schematic_analog" "LVSschematic" "schematic")
cdlSimStopList = '("auCdl")
;;;;;; END Of Configulation for Framboise ;;;;;;;;;;
if( isFile( "./simrc.local" ) then load( "./simrc.local" ) ) 

simViewList = '("hspiceD" "spice" "cmos_sch" "cmos.sch" "schematic" "veriloga" "spiceText")
simStopList = '("hspiceD" "spice" "veriloga" "spiceText")

Reply
  • ZaraF
    in reply to Andrew Beckett

    Thanks for the reply. 

    1. I am not using the Config view. I am directly simulating a schematic view. 

    2. I am not sure how to check that ADE has the right view list. If you are referring to ADE/setup/environment the switch view list before running the simulation is: "spectre cmos_sch cmos.sch schematic veriloga ".

    3. When I run cdswhich .simrc, I get the following message:

     Info (cdswhich): '.simrc' found at: ./.simrc

    4. The .simrc file is available in my working directory and I have attached the file to this post.

    It looks like the view list is being overridden but it is not clear to me why and who is doing that. Any thoughts?

    The interesting thing is that I only get this error when I have a component in the schematic that does not have a Hspice view for example the "stackup" cell from " rfTlineLib". This is very weird as I am using spectre simulator (when I open ADE, the default simulator is Hspice and I switch it to Spectre before running simulations).

    Fullscreen simrc.txt Download 
    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;; Configulation for Verilog netlist
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
simVerilogNetlistExplicit = 't
hnlVerilogNetlistExplicit = 't
hnlVerilogNetlistBehavioralExplicit = 't
hnlVerilogNetlistNonStopCellExplicit = 't
;when(simSimulator=="verilog" hnlRegPostNetlistTrigger('SdVerilogPP))
; ---- for RTL Level verilog netlist extraction
verilogSimViewList = '("functional" "schVeri" "verilog70" "verilog" "schematic" "symbol")
verilogSimStopList = '("verilog70" "verilog" "functional" "symbol")

; ---- for Gate Level verilog netlist extraction
;verilogSimViewList = '("functional" "schVeri" "verilog70" "verilog" "schematic" "symbol")
;verilogSimStopList = '("verilog70" "verilog" "functional")


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;; Configulation for Spice netlist
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

simReNetlistAll = t
simVerilogDropPortRange = nil
simVerilogPwrNetList = '("VDD!" "VEXT!" "VEXTQ!")
simVerilogGndNetList = '("VSS!")
simVerilogSimTimeValue = 1
simVerilogSimTimeUnit = "ns"  
simVerilogSimPrecisionValue = 1
simVerilogSimPrecisionUnit = "ns"
simVerilogBusJustificationStr = "U"
simVerilogTestFixtureFlag = 'nil
simVerilogHandleSwitchRCData = 't
hnlVerilogIgnoreTerm = t

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;  Definition of Net Maping 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;hnlMapNetInName = list("*" '("+" nil) '("(" nil) '(")" nil) '("," nil) '("." nil) '("$" nil) '("[" nil) '("]" nil) '("!" nil))
;hnlMapNetInName = list("*" '("+" nil) '("(" nil) '(")" nil) '("," nil) '("." nil) '("$" nil) '("[" nil) '("]" nil) '("<" "_") '(">" nil) '("!" nil))

;hnlMapNetFirstChar = list("*"
;        '("+" "n")      '("(" "n")      '(")" "n")      '("," "n")      '("." "n")
;        '("$" "n")      '("[" "n")      '("]" "n")      
;        '("!" "n")
;        '("0" "n0")     '("1" "n1")     '("2" "n2")     '("3" "n3")     '("4" "n4")
;        '("5" "n5")     '("6" "n6")     '("7" "n7")     '("8" "n8")     '("9" "n9")
;        )
;hnlMapNetInName = list("*"
;        '("+" nil)      '("(" nil)      '(")" nil)      '("," nil)      '("." nil)
;        '("$" nil)      '("[" nil)      '("]" nil)      
;        '("!" nil)
;        )
;
;
;hnlMapInstFirstChar = list( "*"
;        '("+" "")       '("(" "")       '(")" "")       '("," "")       '("." "")
;        '("$" "")       '("[" "")       '("]" "")       '("_" "_")
;        '("!" "")       '("|" "|")
;        )
;
;hnlMapInstInName = list( "*"
;        '("+" nil)      '("(" nil)      '(")" nil)      '("," nil)      '("." nil)
;        '("$" nil)      '("[" nil)      '("]" nil)      
;        '("!" nil)
;        )


hnlMaxNameLength = 200
hnlMaxLineLength = 128

; The following three options added based on 2x 64GEX3 simrc
vlogExpandIteratedInst = t

vlogifVicSVTextCellViewList = (list "systemVerilogText" "text.v")
auCdlCDFPinCntrl=t
cdlSimViewList = '("auCdl" "schematic_analog" "LVSschematic" "schematic")
cdlSimStopList = '("auCdl")
;;;;;; END Of Configulation for Framboise ;;;;;;;;;;
if( isFile( "./simrc.local" ) then load( "./simrc.local" ) ) 

simViewList = '("hspiceD" "spice" "cmos_sch" "cmos.sch" "schematic" "veriloga" "spiceText")
simStopList = '("hspiceD" "spice" "veriloga" "spiceText")

Children
  • Andrew Beckett
    in reply to ZaraF

    OK, that explains it. The two lines:

    simViewList = '("hspiceD" "spice" "cmos_sch" "cmos.sch" "schematic" "veriloga" "spiceText")
    simStopList = '("hspiceD" "spice" "veriloga" "spiceText")

    are the offending lines. The reason why it probably works with components from the PDK is that I expect they have an hspiceD view for each component (I'm not familiar with PDKs from PSMC, but that's what I'd guess). When you get to using rfTlineLib, then this is not intended to work with HSPICE, and so there's no hspiceD stopping view available.

    Somebody has created this .simrc file in your environment - you probably should speak to your CAD team to find out why that's being done - it seems rather cavalier. Maybe the PDK itself adds it, but it seems unlikely as it's also setting stuff related to Verilog netlisting (which PDKs wouldn't normally care about).

    What's even more annoying is that there's code near the end to load a "simrc.local" file from the working directory which might allow you to override things - but unfortunately the simViewList/simStopList is set after that has been loaded, so that's going to clobber any settings you make. This is a mess - I'd be tempted to just move the file aside (hopefully it won't come back due to something in your system) and see whether that solves it - and then ask questions as to why it's there!

    Andrew

  • ZaraF
    in reply to Andrew Beckett

    Thanks Andrew. I moved that file and the problem is solved. The CAD team has probably added that file in my working directory. 

    Just out of curiosity, what setting are set by the simrc file? I just wanna make sure I am not discarding some other config settings by moving this file.

  • Andrew Beckett
    in reply to ZaraF
    ZaraF said:
    Just out of curiosity, what setting are set by the simrc file?

    The .simrc file is an initialisation file for the Open Simulation System which is the infrastructure used for various netlisters in Virtuoso. It's a SKILL file, and typically sets various special variables used to control particular netlisters. It's commonly used to set special defaults or options for the Verilog netlister (the example you had included many such settings), but there are also special variables for the CDL netlister plus some generic settings - including the ability to control name mapping. The file is SKILL and is read at various times during the netlisting flow, so has the opportunity to intercept several things but also break things if not done carefully - particularly if you set generic OSS variables without making them specific to a particular netlister.

    Andrew

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.