phase noise analysis problem

I moved this to a more appropriate forum (it's not a SKILL question). 

abdurrahman0234 said:

But I get error for the long division ratio leads to long simulation.  I get error from the phase noise analysis

The error you show is nothing to do with it being a long simulation - it's a DC convergence issue. The PSS failed because of that.

You'd probably be best contacting customer support via http://support.cadence.com but at the very least sharing the complete spectre log file (spectre.out) would be a start.

Andrew

Dear abdurrahman0234,

abdurrahman0234 said:

But I get error for the long division ratio leads to long simulation.  I get error from the phase noise analysis::

Error found by spectre during IC analysis, during periodic steady state analysis `pss'.
ERROR (SPECTRE-16080): Cannot print DC solution because DC did not converge. Resolve the convergence issue and rerun the simulation.

Just to add a couple of thoughts in addition to Andrew's two suggestions, it appears you are using a layout based netlist (i.e., extracted view based netlist) and from your post you indicate "long division ratio".

1. I don't know if your divider makes use of static or dynamic dividers or whether there is any set or reset input to force the dividers to a known state. If there is no external set or reset signal to force the dividers to a known state at the start of your transient simulation, this is a common source of DC convergence issues. In essence, without a set or reset at the start of the simulation, there are multiple DC operating solutions.  You may need to include sufficient .ic or .ns statements to either force the DC solution or provide a starting point for the DC operating point analysis to achieve DC convergence.

2. You might also just focus on performing a DC operating point analysis . I would recommend you do not spend your time trying to debug DC convergence using a pss/pnoise analysis until you can achieve consistent DC convergence. Once you have a DC solution, you can use it as an initial condition for the pss/pnoise analysis.

3. As a practical suggestion, if you have not included a signal to force the dividers to a known logic state, I might suggest you consider including one. Designing a divider without a means to force a set/reset is not recommended due to testability and, as you have discovered, simulation issues.

4. Finally, the divider topology you have chosen play a role in DC convergence. A DC input clock to a dynamic divider, depending on its topology, may be irrelevant.

Shawn