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Virtuoso SystemVerilog errors

HoWei
HoWei over 2 years ago

Hi,

I am using Virtuoso for AMS simulations with SystemVerilog modules. The modules are not stored in the cellview-folder itself (e.g. cell-name is "tbKernel")  - instead they are in another folder of an SVN working copy. To access those SVN files from the Virtuoso Libmanager, I created symbolic links from the cellview folder "./tbKernel/systemVerilog" to the SVN - e.g. "./tbKernel/systemVerilog/verilog.sv --> ../../svn/testbench/tbKernel.sv". This is working fine for a simple SV module !

Another (more complex) SV file imports modules and packages, some are located in the same SVN folder, others are standard packages such as "cmath". Since the SV files are typically simulated in another environment than Virtuoso (e.g. Questasim), I am sure the syntax is correct and working properly in the other environment.

The "check&save" for this more complex SV file shows the following errors:

 22 package cmath;
 23 import "DPI-C" function real sin(input real x);
 24 endpackage // cmath

 26 import cmath::*;                                   <-- ERROR-1: Package cmath cannot be bound !

 28 // import tbObjPkg::*;                           <-- ERROR-2: Package tbObjPkg cannot be bound !
 29 `include "/...some_path_here.../svn/testbench/tbObjPkg.sv"  <-- absolut path fixes ERROR-2, but is not a solution - I need relative pathes to keep consistency in the SVN for other environments.

799 //always @ (*) begin                           <-- ERROR-3: Using "*" grays out the rest of the code until the next "*" 
800 always @ (/*AUTOSENS*/) begin      <-- this fixes ERROR-3
801 if (sdEnable==1) begin
802 sdin1 = sdInterface1.sdout_sd;

Now my questions on those errors are:

ERROR-1: This is a package that comes with the tool - how can I make it available and bind it in Virtuoso - is there a dedicated entry in the "hdl.var" file required (we are using XCELIUM for AMS simulations) ?

ERROR-2: How can I make the tool looking in the same folder (relative pathes) for modules/files to be included - especially with my linked "verilog.sv" to the SVN folder ?  

ERROR-3: Why does "*" work in the pure digital environment (e.g. questasim) but not in the Virtuoso environment ?

Thanks in advance for some suggestions !

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  • Saloni Chhabra
    Saloni Chhabra over 2 years ago

    Hi,

    1. For working with packages, you can use HDL Package setup. It is a very neat way of working with packages in Virtuoso. You can can find a working example here:

    https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w00000ADvAJEA1&pageName=ArticleContent

    2. I understand you need -incdir to locate the files during check&save. You can add the below to hdl.var:

    DEFINE XRUNOPTS -incdir /path/to/directory1 -incdir /dir2/..

    3. always @(*) greys out the code in Virtuoso text editor, but the code compiles and syntax errors (if any) are caught as well. You can use @( * ) instead to avoid the auto-formatting.

    Regards,
    Saloni

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  • HoWei
    HoWei over 2 years ago in reply to Saloni Chhabra

    Hi Saloni,

    thanks for the quick and crisp answers.

    I tried your proposals, but still I am not able to "check&save" properly. 

    I do have some follow up questions:

    ERROR-1: Do you know where I can get the "cmath" from ?  I assume it is somewhere located in the XCELIUM installation folder / shared libs. I need to include it and want to use either "hdl.var" or the HDL package setup. 

    I found that in "hdl.var" there is an line "DEFINE XRUNOPTS -pgksearch .... " -  can this be used as well for package inclusion ?

    An example would be appreciated.

    ERROR-2: I tested various pathes in "hdl.var", but none of them was successfull. 

    `include "tbObjPkg.sv"   <-- this does not work with "hdl.var" -incdir added to XRUNOPTS  or  XMVLOGOPTS

    1. Will changes in "hdl.var" be visible to the Cadence texteditor immediately, or do I need to reload "hdl.var"  somehow or restart Cadence to get the changes applied ?

    2. As in the original code it is stated "import tbObjPkg::*;" this would mean the comlete package is imported - is this equivalent to "'include "tbObjPkg.sv" - as this "include" would also add the comlete file during compilation ?

    ERROR-3:  I just found that /*AUTOSENSE*/ throws an syntax error as well.: "Error: illegal expression primary [4.2(IEEE)]. 

    It appears that /*AUTOSENSE*/ is not Verilog Standard, but instead is a texteditor (emacs) feature only ?

    The problem with * and /*AUTOSENSE*/ is, that without any error-free "check&save" I will not be able to auto-generate a symbol view from the SV view.

    Any further ideas are very welcome.

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  • Saloni Chhabra
    Saloni Chhabra over 2 years ago in reply to HoWei

    Hi,

    I think it'll be much easier to resolve your setup issues if you worked with a local AE. Please contact Cadence customer support.

    I'll try to answer some of your questions here:

    1. DEFINE XRUNOPTS -pkgsearch should work as well, but HDL package setup makes working with packages much easier.

    2. You are creating your own package called 'cmath', so are you asking if we ship something similar? We don't provide one in the installation, but the AE you work with can provide you a broader list of math DPI functions you can put in your math package (like cmath).

    3. hdl.var will be read automatically an active IC session, so you don't need to re-start. If you've added DEFINE XMVLOGOPTS -incdir, it should reflect in the xmvlog log file generated when you run check and save.

    4. The difference between `include and import comes from the language and you can find a lot of information if you search this on Google. `include inserts (like copy and paste) the code, while import is used to make all/selected contents from a package visible. 

    5. I may not have completely understood what AUTOSENS does, but in Virtuoso text editor (* is seen as an attribute, hence the graying. But this is only a display behaviour and I will speak to R&D about fixing this. The compiler does not see @(*) as an error. Instead of (*), you can write (  *  ) i.e. put white space characters before and after *, then nothing will be grayed out in Virtuoso.

    Regards,

    Saloni

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  • Saloni Chhabra
    Saloni Chhabra over 2 years ago in reply to HoWei

    Hi,

    I think it'll be much easier to resolve your setup issues if you worked with a local AE. Please contact Cadence customer support.

    I'll try to answer some of your questions here:

    1. DEFINE XRUNOPTS -pkgsearch should work as well, but HDL package setup makes working with packages much easier.

    2. You are creating your own package called 'cmath', so are you asking if we ship something similar? We don't provide one in the installation, but the AE you work with can provide you a broader list of math DPI functions you can put in your math package (like cmath).

    3. hdl.var will be read automatically an active IC session, so you don't need to re-start. If you've added DEFINE XMVLOGOPTS -incdir, it should reflect in the xmvlog log file generated when you run check and save.

    4. The difference between `include and import comes from the language and you can find a lot of information if you search this on Google. `include inserts (like copy and paste) the code, while import is used to make all/selected contents from a package visible. 

    5. I may not have completely understood what AUTOSENS does, but in Virtuoso text editor (* is seen as an attribute, hence the graying. But this is only a display behaviour and I will speak to R&D about fixing this. The compiler does not see @(*) as an error. Instead of (*), you can write (  *  ) i.e. put white space characters before and after *, then nothing will be grayed out in Virtuoso.

    Regards,

    Saloni

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  • HoWei
    HoWei over 2 years ago in reply to Saloni Chhabra

    Hi Saloni,

    I opened a ticket at the Cadence support for this issues.

    I already found that the HDL Package Setup allows me to specifiy files to be included and I am wondering if complete folders can also be added as a searchpath.

    I hope to get feedback soon from an AE, but in the meantime I found another issue, and maybe you have an idea:

    78 typedef class sigmadelta;   <-- Error: The class specified was never delcared.  but as you see, it is declared later on line 908.

    ....

    908 class sigmadelta;

    909        real analogIn;

    Any idea why the editor does not find the class definition ?

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  • Saloni Chhabra
    Saloni Chhabra over 2 years ago in reply to HoWei

    That's because you have a typo - line 78 says 'sigmadelta' , while line 908 says 'signamdelta'.

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  • HoWei
    HoWei over 2 years ago in reply to Saloni Chhabra

    Hi Saloni,

    that was a typo only in this forum text - it is correct inside the code.

    I found that the text-editor (maybe even xcelium) only finds the class declaration if it is located within the "module/endmodule" definition.

    If the class definition is outside the module-definition, but inside the same file, it will not find the class declaration.

    If the class-definition is in another file, which is included via the "include" statement, it also does not find the class declaration (even if the respective file is correctly listed in the AMS-IncludeOptions-FileList).

    All these things are no issue if the code is executed within questasim and I assume this is all according to the systemVerilog standard.

    I am wondering how to convice the Cadence Virtuoso/Xcelium environment to accept such a code-structure ?

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  • HoWei
    HoWei over 2 years ago in reply to Saloni Chhabra

    The above mentioned /*AUTOSENSE*/ commands are Emacs features and will not apply to any systemVerilog standard. Was a misunderstanding from my side.

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  • Saloni Chhabra
    Saloni Chhabra over 2 years ago in reply to HoWei

    Here's an example code that compiles fine for me in Virtuoso Text Editor - can you check if this works for you? And does this represent what you are trying to do? 

    //systemVerilog HDL for "testLib_ams", "typedef_class" "systemVerilog"

    typedef class c2;
    //class-1
    class c1;
    c2 c;     //using class c2 handle before declaring it.
    endclass

    //class-2
    class c2;
    c1 c;
    endclass

    module typedef_class;
    initial begin
    c1 class1;
    c2 class2;
    $display("Inside typedef_class");
    end
    endmodule

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  • HoWei
    HoWei over 2 years ago in reply to Saloni Chhabra

    Not exaclty the code I mean, but referring to your example, this works:

    module typedef_class;
    typedef class c1;
    c1 class1;
    class c1;
    endclass
    endmodule

    This does not work:

    module typedef_class;
    typedef class c1;
    c1 class1;
    endmodule

    class c1;
    endclass

    It complains that the class declaration is outside of the module.

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  • Saloni Chhabra
    Saloni Chhabra over 2 years ago in reply to HoWei

    Thanks for the code, the error comes from Xcelium (not Virtuoso). Let me see if I can get more information on this.

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  • HoWei
    HoWei over 2 years ago in reply to Saloni Chhabra

    According to the XCELIUM AGILE SystemVerilog reference manual, the classes cannot be declared globally (yet).

    See under "Classes-Declaring a Class datatype" (why is there no chapter number given in the manual ?) !

    I see this as a significant limitation for code-compatibility between tools for SystemVerilog.

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  • HoWei
    HoWei over 2 years ago in reply to HoWei

    One more thing is, that the SV code uses " 'include " statements, which I do not find in the Cadence SystemVerilog reference manual under "Compiler Directives" or any other chapter.

    But I think it is a standard thing to use.  

    Do you have a reference where "  'include  " is used and documented ?

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  • Saloni Chhabra
    Saloni Chhabra over 2 years ago in reply to HoWei

    I can see chapter numbers in SV reference guide (Classes are in Chapter 9). 

    But I think at this point, it's best you contact Cadence Customer Support to get more information on working with Classes.

    Regards,
    Saloni

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