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  3. STB Analysis: Invalid instance name

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STB Analysis: Invalid instance name

fyoh
fyoh over 2 years ago

Hi all,

The same error in this post: Spectre stability analysis with active device as probe - Custom IC Design - Cadence Technology Forums - Cadence Community

I have a testbench where I run STB analysis and which has been working until the problem I'm about to describe appeared. The testbench has an amplifier block and a stbprobe block. The diffstbprobe STB probe is in the default schematic view of the stbprobe block and I can see it in the netlist. As I told you, it has been working and the testbench still works for transient analysis. When I run the STB analysis, I am seeing this error whose cause I don't understand.

I tried the following:

1. Initially, the test was to  launch stb using actimes & acnames,  it had been working. The tran alone still works. However, at the simulation time when STB used to be launched, I see the above error.

2. Tried with diffstbprobe

2. Change of probe name didn't help.

3. I recently did PDK change. An update and restart of cadence did not solve the problem. There are other tests in the same testbench which use the same cell block which are working ok.

4. It works when the diffstbprobel_gnd is outside the STB probe in the main schematic. 

Software: Virtuoso ICADVM20.1-64b.500.29

Any idea how to fix this.

Thank you.

Fyoh

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  • ShawnLogan
    ShawnLogan over 2 years ago

    Dear Fyoh,

    fyoh said:
    I have a testbench where I run STB analysis and which has been working until the problem I'm about to describe appeared. The testbench has an amplifier block and a stbprobe block. The diffstbprobe STB probe is in the default schematic view of the stbprobe block and I can see it in the netlist. As I told you, it has been working and the testbench still works for transient analysis. When I run the STB analysis, I am seeing this error whose cause I don't understand.

    and

    fyoh said:
    3. I recently did PDK change.

    I do not know the extent of the PDK change (i.e, different technology node, an update to an existing PDK, etc...). However, what I might suggest is you step back to your prior PDK and generate a netlist. Re-create the netlist for the transient run with STB analyses at specific time points. Save this netlist and its input.scs file to something like "former_netlist" and "former_input.scs". From your Forum post, I think this input.scs file should simulate correctly. Is this correct?

    Now, switch to your current PDK (which you term "PDK change"). Re-create the netlist and input.scs file for the transient run with STB analyses at specific time points which no longer simulates correctly. Compare the two netlists (files "former_netlist" and "netlist" as well as "former_input.scs" and "input.scs") using a UNIX utility such as tkdiff. There has to be a difference between the two sets of files to cause one to simulate correctly and one to fail.

    This also assumes your run commands are the same. You can check this by comparing the "runSimulation" files in the two respective netlist directories.

    fyoh said:
    There are other tests in the same testbench which use the same cell block which are working ok.

    What do you mean by this statement Fyoh? Are the "other tests" performing the same transient analysis with intermediate STB analyses at some times within the transient analysis? Or, do the "other tests" include analyses other than a STB analysis?

    Shawn

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  • fyoh
    fyoh over 2 years ago in reply to ShawnLogan

    Dear Shawn,

    Thank you for your response.

    It is an update to an existing PDK, but still working on the same technology. I will try your suggestion on comparing the netlists although it involves many steps in the environment I am working. I don't think the run commands have any difference, but I will give it a look. 

    My initial guess was somehow the STB probe buried deep in a hierarchy was creating a problem. I have seen this error whenever the probe is not at top schematic view of the testbench. Let me describe the arrangement a bit more.  

    The other tests that I mentioned in the original post are for running other analyses (PAC, PNOISE, AC and Tran). They all share the same circuit block I am trying to verify, but some are in open loop and others in closed-loop. It is a switched-capacitor amplifier circuit.

    The problem that I am sharing with you occurs when I run the closed loop switched-capacitor amplifier STB simulation. As I have to simulate both common-mode and diff. modes, I have a circuit block, let's call it probe_block, which connects the diff. output and common-mode outputs in different ways depending on the simulation to be launched. Basically, I select different schematic views of this probe_block to place the STB probe on the CMFB loop or the main feedback loop. Thus, I have both the outputs of the amplifier and the CMFB circuit block inputs connected to this probe_block.

    As I mentioned, the simulation works when I place the probe on the main testbench, i.e., by ignoring the probe_block. I see the error above when I try to use this probe_block. It is not a complicated probe_block and I had been using it without problem with the SC amplifier. The other reason I don't think  it is the cause of this problem is that I see the above "invalid instance error" when I try to place an STB probe down in a hierarchy. 

    My question is: it possible that multiple loops that are created due to a non-flat circuit implementation limit the usage of the STB analysis to probes placed only on the top of the testbench schematic view? The reason I am asking this is because I see the same error whenever I try to simulate internal loops in the OTA of the SC amplifier.

    Thanks.

    Fyoh

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  • ShawnLogan
    ShawnLogan over 2 years ago in reply to fyoh

    Dear Fyoh,

    Thank you for reading my comment and your added circuit topology information. The latter is helpful and provided a possible clue as to a possible source of your simulation failure.

    fyoh said:
    As I mentioned, the simulation works when I place the probe on the main testbench, i.e., by ignoring the probe_block. I see the error above when I try to use this probe_block.

    I did find a limitation on the use of diffstbprobe in the Troubleshooting note at URL:

    support.cadence.com/.../ArticleAttachmentPortal

    where the its terminals must not be terminals of a block. If your "probe_block" has the stability probes connected directly to the terminals of "probe_block" you may be impacted by this limitation. This may make sense in that you mention several times that using the probe at the top level of your schematic does not result in an error.

    Is there any chance your "probe_block" has either of its internal probe terminals connected as "probe_block" I/O?

    Shawn

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  • Andrew Beckett
    Andrew Beckett over 2 years ago in reply to ShawnLogan
    ShawnLogan said:

    I did find a limitation on the use of diffstbprobe in the Troubleshooting note at URL:

    support.cadence.com/.../ArticleAttachmentPortal

    where the its terminals must not be terminals of a block

    Shawn,

    The only limitation I'm aware of is if you use the newer capability (only available with stb; not there with pstb or hbstb yet) to perform differential stability checks without actually inserting a diffstbprobe instance; in that case you can only specify the terminals of a leaf device. If you've actually inserted a diffstbprobe, then there's no limitations on it being connected to the pins of a block or not (I can't see why the simulator could have a problem with that).

    Fyoh,

    It's very hard to see what your issue is here. The only thing I can imagine is that there's some switch view list issue where the probe is not being netlisted, or that your setup is wrong. You've given so little actual information on how you've set things up or what the netlist looks like that it's near-impossible to help (we're all having to guess).

    I suggest you contact customer support (create a case).

    Andrew

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  • ShawnLogan
    ShawnLogan over 2 years ago in reply to Andrew Beckett

    Dear Andrew,

    Andrew Beckett said:
    The only limitation I'm aware of is if you use the newer capability (only available with stb; not there with pstb or hbstb yet) to perform differential stability checks without actually inserting a diffstbprobe instance;

    Thank you, once again, for correcting my misunderstanding from reading the Troubleshooting article I referred to. I am humbled, once again!

    Shawn

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  • fyoh
    fyoh over 2 years ago in reply to Andrew Beckett

    Hi Andrew,

    I have opened a case.

    Thanks.

    Fyoh

    Case# 46673872: The owner of the case was able to reproduce the issue and error. 

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