Home
  • Products
  • Solutions
  • Support
  • Company
  • Products
  • Solutions
  • Support
  • Company
Community Forums Custom IC Design PSS ANALYSİS

Stats

  • Replies 2
  • Subscribers 123
  • Views 199
  • Members are here 0

PSS ANALYSİS

abdurrahman0234
abdurrahman0234 2 months ago

hello everyone,

While I run post layout pss analysis for the divider (divide by 250), I get insufficient memory error. server ram is the 128G. I reduced PEX size to 10M  but  RAM is still not enough. I use Spec X for the simulation. How can I achieve pss analysis?

Thanks 

  • Reply
  • Cancel
  • Cancel
  • ShawnLogan
    ShawnLogan 2 months ago

    Dearabdurrahman0234,

    abdurrahman0234 said:
    While I run post layout pss analysis for the divider (divide by 250), I get insufficient memory error. server ram is the 128G. I reduced PEX size to 10M  but  RAM is still not enough. I use Spec X for the simulation. How can I achieve pss analysis?

    It is highly likely the reason you are running out of memory is the ratio between your input and output frequencies (250). There is an article that speaks to this issue at

    https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od000000056dyEAA&pageName=ArticleContent

    and it notes that a memory allocation of over 150 GB is reasonable for a divider ration less than your value of 250. Hence, it makes sense that your machine resources are insufficient for this simulation.

    1. I am not sure what you are trying to measure with this type of simulation. Put another way, with a divider of 250, the noise of the divider itself is going to be miniscule on a unit interval basis.This, alone, will push the accuracy of the simulation to its limits. Perhaps if you provide the motivation for your interest in this simulation, it might allow others to suggest an alternative.

    2. Usually, for both testability and simulation reasons, long divider chains are purposefully broken into a series of smaller dividers. As an example in your case with a divider of 250, it might be set to say two divide-by-five and 1 divide by 10 elements. This reduces testing time and simulation time. Is this something you or your manager have considered?

    Shawn

    • Cancel
    • Up 0 Down
    • Reply
    • Cancel
  • abdurrahman0234
    abdurrahman0234 1 month ago in reply to ShawnLogan

    İ try to get Phasenoise analysis.

    For broke the circuit, ıt may not be possible because of the feedback wires except input signal for the divider chains. You means that we divide two times input  without broken circuit by using noise file from the result of the first division?

    • Cancel
    • Up 0 Down
    • Reply
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2023 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information