RLC parasitic extraction type for post-layout simulation

Dear Senan,

Senan said:

I would know from you about the neccessity of of performing the RLC parasitic  extraction.

Please allow me to add a thought or two...

The two questions in my mind, Senan, are how important are inductances to the performance of your circuit relative to its requirements and are its layout constraints such that they will introduce significant inductances? If either of these answers are yes, then you likely need to consider a way to include inductances in your post-layout simulation. However, this does not necessarily mean you need an "RLC extraction". The process may have changed, but in my experiences generating RLC extractions the extraction that includes inductive elements does not encompass the entire layout. Only portions of the layout where inductances are deemed important contain inductive elements. As such, the generation of an RLC extraction is far more time intensive as one must determine exactly which layout regions to include. As I mentioned, the process may be less tedious now.

However, in many designs for which I was responsible, I includes inductive elements by using S-parameters or discrete inductances as black-box elements to model structures simulated in a 2.5/3D EM simulator. Although not an "RLC extarction",  accurate simulation results for circuits with inductive sensitivities were obtained.

I thought I might add my comments Senan...I am sure other experts who monitor this Forum will be able to comment too.

Shawn

Thank you very much Shawn for your reply.

Yes I can understand completely your comments, for my case and based your points, RLC exctraction will be useful for me if I could include the package model which I still missing in my simulations. After receiving our fabricated chip, I have realized how much is important to simulate the inductance effect including the package leads and also by modelling the inductance of the bonding wires.

Thank you once again Shawn

Regards

Dear Senan,

Senan said:

Yes I can understand completely your comments,

Great! I am glad they made some sense to you

Senan said:

After receiving our fabricated chip, I have realized how much is important to simulate the inductance effect including the package leads and also by modelling the inductance of the bonding wires.

I agree that this is an excellent idea to increase the accuracy of your transient simulations. Good luck Senan!

Shawn

Senan said:

RLC exctraction will be useful for me if I could include the package model which I still missing in my simulations

I don't think that would including the package model would imply that you need to do RLC extraction on-chip. Normally using RLC extraction is useful if you have high-speed interconnect on-chip, and I doubt it would be necessary at the frequencies you're talking about. As Shawn suggested, critical nets could be extracted using an electromagnetic solver such as EMX (and this can be combined with Quantus RC extraction if using the EM assistant in Virtuoso Layout Suite EXL). However, I wouldn't anticipate this as being necessary at the frequencies you're dealing with since the on-chip parasitic inductances are likely to be small. Package and board modelling is more likely to be significant.

Andrew

Dear Shawn and Andrew,

Thank you very much both  for your reply,

It is all you made it clrear for me.

I will focus on modelling the package with equivalent circuit model on my circuit pads, I presume that my IC packaging house should have the model for the package I have selected, and approximation of the  wire bond equivalent inductances which for sure depends on its length,

Thank you once again and best regards