• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. cadence simulation in digital IC design

Stats

  • Locked Locked
  • Replies 2
  • Subscribers 125
  • Views 7455
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

cadence simulation in digital IC design

blossom
blossom over 2 years ago

This is my entire program


module fourbit_multi(a,b,c,clk);
input [3:0]a,b;
input clk;
output [7:0]c;
wire s1,s2,s3,s4,s7;
wire s5;
wire s6,s8,s9,s10;
always@(posedge clk)
twobit_multi a1(a[1:0],b[1:0],s1);
twobit_multi a2(a[3:2],b[1:0],s2);
twobit_multi a3(a[1:0],b[3:2],s3);
twobit_multi a4(a[3:2],b[3:2],s4);
assign c[1:0]=s1[1:0];
assign s7={2'b00,s1[3:2]};
fourbit_adder a5(s2,s7,s5[3:0],s5[4]);
assign s8={2'b00,s3[3:0]};
assign s9={s4[3:0],2'b00};
sixbit_adder a6(s8,s9,s6);
assign s10={1'b0,s5};
sixbit_adder a7(s6,s10,c[7:2]);
endmodule

module fourbit_adder(x,y,z,cout);
input [3:0]x;
input [3:0]y;
output [3:0]z;
output cout;
wire [2:0]p;
half_adder p1(z[0],p[0],x[0],y[0]);
full_adder p2(z[1],p[1],x[1],y[1],p[0]);
full_adder p3(z[2],p[2],x[2],y[2],p[1]);
full_adder p4(z[3],cout,x[3],y[3],p[2]);
endmodule

module sixbit_adder(k,l,m);
input [5:0]k;
input [5:0]l;
output [5:0]m;
wire [5:0]n;
half_adder q1(m[0],n[0],k[0],l[0]);
full_adder q2(m[1],n[1],k[1],l[1],n[0]);
full_adder q3(m[2],n[2],k[2],l[2],n[1]);
full_adder q4(m[3],n[3],k[3],l[3],n[2]);
full_adder q5(m[4],n[4],k[4],l[4],n[3]);
full_adder q6(m[5],n[5],k[5],l[5],n[4]);
endmodule


module twobit_multi(u,v,w);
input [1:0]u;
input [1:0]v;
output wire [3:0]w;
wire d,e,f,g;
and u1(w[0],u[0],v[0]);
and u2(d,u[0],v[1]);
and u3(e,u[1],v[0]);
half_adder u4(w[1],f,d,e);
and u5(g,u[1],v[1]);
half_adder u6(w[2],w[3],f,g);
endmodule

module half_adder(sum,carry,q,r);
input q,r;
output sum,carry;
and m1(carry,q,r);
xor m2(sum,q,r);
endmodule

module full_adder(o,t,h,i,j);
input h,i,j;
output o,t;
wire t1,t2,t3;
xor r1(o,h,i,j);
and r2(t1,h,i);
and r3(t2,i,j);
and r4(t3,h,j);
or r5(t,t1,t2,t3);
endmodule

Red colour line shows an error like

twobit_multi a1(a[1:0],b[1:0],s1);
              |
ncvlog: *E,MISEXX (/home/cadence/Desktop/PY/bakeup digital design/vedicm4/vedicm.v,11|14): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].

  • Cancel
Parents
  • Saloni Chhabra
    Saloni Chhabra over 2 years ago

    Hi,

    What is the purpose of always statement in this code? That should be removed or the always block should be written correctly.

    always@(posedge clk)
    twobit_multi a1(a[1:0],b[1:0],s1);

    Regards,
    Saloni

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • Saloni Chhabra
    Saloni Chhabra over 2 years ago

    Hi,

    What is the purpose of always statement in this code? That should be removed or the always block should be written correctly.

    always@(posedge clk)
    twobit_multi a1(a[1:0],b[1:0],s1);

    Regards,
    Saloni

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
  • blossom
    blossom over 2 years ago in reply to Saloni Chhabra

    Ok mam. Thank you

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information