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Instance of Design Unit is Unresolved

Hongming Lyu

Hello,
I am using NC-Verilog Integration plugined in Virtuoso 6.1.8 to generate Verilog netlist file.
When I simulated the netlist. The system telled me Elaboration Failed.
Please help me find Verilog representation of above design units and tell me how to use them in compiling time.
Any help in finding solution will be appreciated.

  • Andrew Beckett

    That's expanding the hierarchy of a schematic down to transistor level, and you don't have a Verilog model of the transistor. What are you expecting it to do in this case? Note that the Verilog integration is not going to perform a mixed-signal simulation; you'd need to give some information on a model for the nmosmvt2v and pmos3v (etc) devices - perhaps some kind of switch model? It won't find this magically unless you provide it.

    Overall, what is your goal here? Do you really want to simulating this at transistor level (given that Incisive/Xcelium is not a transistor-level simulator).

    Andrew

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