Stats

  • Locked Locked
  • Replies 1
  • Subscribers 125
  • Views 12127
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Instance of Design Unit is Unresolved

Hongming Lyu

Hello,
I am using NC-Verilog Integration plugined in Virtuoso 6.1.8 to generate Verilog netlist file.
When I simulated the netlist. The system telled me Elaboration Failed.
Please help me find Verilog representation of above design units and tell me how to use them in compiling time.
Any help in finding solution will be appreciated.

  • That's expanding the hierarchy of a schematic down to transistor level, and you don't have a Verilog model of the transistor. What are you expecting it to do in this case? Note that the Verilog integration is not going to perform a mixed-signal simulation; you'd need to give some information on a model for the nmosmvt2v and pmos3v (etc) devices - perhaps some kind of switch model? It won't find this magically unless you provide it.

    Overall, what is your goal here? Do you really want to simulating this at transistor level (given that Incisive/Xcelium is not a transistor-level simulator).

    Andrew

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.