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Issue with autogenerating multiple Verilog-A views in same cell

muheicdesign

Dear Cadence Forum,

I've created a Python script that autogenerates Verilog-A models for discrete capacitors that model their non-linearities due to DC bias degradation. 
The python script attempts to create multiple verilog-a files and the symbol. My goal is that is should be possible to just load in the cell view in the library manager and then work.

The Python script generates multiple verilog-a views for the same cell. I've tried to follow the adequate file structure that Cadence require for the Library Manager to acknowledge the cell. (creating a folder the symbol with the relevant files, e.g. symbol/ and for the veriloga view e.g. veriloga/). 

The desired structure is:

CELL: {{capacitor_name}}

VIEW: symbol (consisting of the symbol files)
VIEW: veriloga (consisting of the veriloga.va file and the master.tag file)
VIEW: veriloga_rc (consisting of another version of the veriloga.va file and a master.tag file)
VIEW: verilog_rlc (consisting of another version of the veriloga.va file and a master.tag file)

 

The script functions well for the view named just "veriloga". After I import the library with the library manager, I can open the veriloga view with the text editor from the library manager and when I save, the netlist.oa and data.dm files are generated automatically. Great.
But for the two other views, which are veriloga files, but not named "veriloga", the library manager cannot find it. The CIW window gives the following error message, when I try to open these with the Library Manager:

*WARNING* ddsServOpen: Unable to find the master file for capacitor_models/GRM21BC71E106KE11/veriloga_rc.

I know that you get a warning message, when you go file -> new --> Cell View and create a veriloga TYPE, with a cell name different from veriloga, but the library manager simply asks you if you want to use veriloga TYPE for the file. 

The reason for the multiple veriloga views is because I want to easily switch between the different complexity of the views using a config file later.

My fear is that there is some reference stored in the binary data.dm og netlist.oa files, that I need to be correct.

Any suggestions on fixing this. I really don't want to sit and create the view names for the veriloga_rc and veriloga_rlc manually with the library manager and then copy the veriloga code into these files. There must be a better way!

If it is relevant the python script is located on github here:
https://github.com/muheicdesign/generate_capacitor

Thank you in advance.

Parents
  • Andrew Beckett

    The problem is (from a very quick glance at your Python code) is that the file inside the view directory must be called veriloga.va and not (say) veriloga_rc.va. The file name of the master file is what is used by the registry in Virtuoso to determine the view type which is how we know how to deal with it. The view name (i.e. the view directory) can be called whatever you want - it's just the file itself must be called veriloga.va .

    You can also get the netlist.oa generated by calling the SKILL function amsUpdateTextviews() with relevant arguments - you might want to consider that approach rather than having to open and save with the editor after generating them.

    I did wonder about using the utility we provide called cdsTextTo5x to import the VerilogA code, but I then realised that this utility doesn't support (as far as I can see) VerilogA code - possibly because it's not that common for this to be generated outside of Virtuoso by most of our users, whereas importing external Verilog, VHDL, Verilog-AMS, SystemVerilog etc is much more common.

    BTW - your post was moderated originally because of the GitHub URL (sorry!)

    Regards,

    Andrew

Reply
  • Andrew Beckett

    The problem is (from a very quick glance at your Python code) is that the file inside the view directory must be called veriloga.va and not (say) veriloga_rc.va. The file name of the master file is what is used by the registry in Virtuoso to determine the view type which is how we know how to deal with it. The view name (i.e. the view directory) can be called whatever you want - it's just the file itself must be called veriloga.va .

    You can also get the netlist.oa generated by calling the SKILL function amsUpdateTextviews() with relevant arguments - you might want to consider that approach rather than having to open and save with the editor after generating them.

    I did wonder about using the utility we provide called cdsTextTo5x to import the VerilogA code, but I then realised that this utility doesn't support (as far as I can see) VerilogA code - possibly because it's not that common for this to be generated outside of Virtuoso by most of our users, whereas importing external Verilog, VHDL, Verilog-AMS, SystemVerilog etc is much more common.

    BTW - your post was moderated originally because of the GitHub URL (sorry!)

    Regards,

    Andrew

Children
  • Andrew Beckett
    in reply to Andrew Beckett

    Markus - I joined your two posts (the second one confirmed what I saw in your Python code).

    Regards,

    Andrew

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