PSS for PLL loop

Dear RaghavendraN,

After reading your post, I am not sure you have included enough information to provide a definitive answer. However, there a a number of possible explanations for your observation that come to mind.

1. First, the use of a pss analysis followed by a pnoise simulation to estimate the phase noise performance of a phase-locked loop is not recommended by Cadence. Please see my comments regarding its use that I wrote to you in your Forum post from 17 days ago at URL:

https://community.cadence.com/cadence_technology_forums/f/mixed-signal-design/56706/pll-pss-simulation-in-spectre

2. The fact that your pss solution converged does not guarantee that the phase-locked loop is phase-locked. How are you verifying that the solution provided by pss represents a state of phase-lock from which its phase noise may be accurately estimated?

3. Unlike an analog phase detector, the PFD is sampled phase detector. As such, if your reference clock frequency is fref, any reference noise frequencies above fref/2 will exceed the Nyquist frequency and hence will alias to lower frequencies. Are you sure the "1/s(integrator) behaviour (sic)" is not a result of aliasing of your input reference noise? You did not include the relationship between your reference noise bandwidth and your reference frequency, and hence I wanted to alert you to the issue. This is the motivation for using a Z-domain analyses to accurately model PFD loop behavior in lieu of its "approximate" linear analysis.

4. Have you tried to verify your results using a transient noise simulation after determining an appropriate loop settling time with a conventional transient analysis?

There are many other possibilities, but without more details on your effort and simulator settings, I do not want to waste your time with useless suggestions RaghavendraN.

Shawn

ShawnLogan said:

1. First, the use of a pss analysis followed by a pnoise simulation to estimate the phase noise performance of a phase-locked loop is not recommended by Cadence. Please see my comments regarding its use that I wrote to you in your Forum post from 17 days ago at URL:

Well, that's news to me (you said this in another post recently, and I was away/busy at the time and was planning to object to it then too). Sure, it's not appropriate for a fractional PLL, and there may be more efficient ways of coming up with the phase noise performance (such as that covered by the RAK we have on PLL simulation, which uses a divide-and-conquer approach to characterise the various blocks), but I'm not sure I'd go as far as saying it wasn't recommended. It might be difficult to converge and costly to simulate, but I wouldn't say it's not recommended. Who is saying this?

ShawnLogan said:

2. The fact that your pss solution converged does not guarantee that the phase-locked loop is phase-locked. How are you verifying that the solution provided by pss represents a state of phase-lock from which its phase noise may be accurately estimated?

It's pretty unlikely that the PSS will converge if it's not phase-locked, as you won't have a steady-state solution. There's a possibility that your VCO might have reached the end of its tuning range (say) but then the VCO output wouldn't be a harmonic of the input frequency, so unlikely to converge. There is a possibility that if the cycle-to-cycle variation is very small that PSS may think its converged when it hasn't (this can happen if you have extremely long time constants), but again this is fairly rare. Of course, one should always check that the results look reasonable.

Andrew

ShawnLogan said:

1. First, the use of a pss analysis followed by a pnoise simulation to estimate the phase noise performance of a phase-locked loop is not recommended by Cadence. Please see my comments regarding its use that I wrote to you in your Forum post from 17 days ago at URL:

Well, that's news to me (you said this in another post recently, and I was away/busy at the time and was planning to object to it then too). Sure, it's not appropriate for a fractional PLL, and there may be more efficient ways of coming up with the phase noise performance (such as that covered by the RAK we have on PLL simulation, which uses a divide-and-conquer approach to characterise the various blocks), but I'm not sure I'd go as far as saying it wasn't recommended. It might be difficult to converge and costly to simulate, but I wouldn't say it's not recommended. Who is saying this?

ShawnLogan said:

2. The fact that your pss solution converged does not guarantee that the phase-locked loop is phase-locked. How are you verifying that the solution provided by pss represents a state of phase-lock from which its phase noise may be accurately estimated?

It's pretty unlikely that the PSS will converge if it's not phase-locked, as you won't have a steady-state solution. There's a possibility that your VCO might have reached the end of its tuning range (say) but then the VCO output wouldn't be a harmonic of the input frequency, so unlikely to converge. There is a possibility that if the cycle-to-cycle variation is very small that PSS may think its converged when it hasn't (this can happen if you have extremely long time constants), but again this is fairly rare. Of course, one should always check that the results look reasonable.

Andrew

Dear Andrew,

Andrew Beckett said:

It might be difficult to converge and costly to simulate, but I wouldn't say it's not recommended. Who is saying this?

I was only quoting Tawna's post at URL:

https://community.cadence.com/cadence_technology_forums/f/rf-design/49390/pss-pnoise-simulation-for-vco-and-pll

"PLLs are difficult to get convergence with in SpectreRF. All signals must be periodic and the circuit must respond periodically, otherwise you won't get convergence.

This is what I recommend to designers:

Simulating PLLs and DLLs are best accomplished with transient/transient noise analysis."

which I believe you just commented on in a similarly themed post. Obviously, I am not in any position to make a "Cadence recommendation" on anything and hope I did not mislead anyone with my statement. I was only trying to interpret Tawna's comments correctly and pass them along.

Andrew Beckett said:

It's pretty unlikely that the PSS will converge if it's not phase-locked, as you won't have a steady-state solution. There's a possibility that your VCO might have reached the end of its tuning range (say) but then the VCO output wouldn't be a harmonic of the input frequency, so unlikely to converge. There is a possibility that if the cycle-to-cycle variation is very small that PSS may think its converged when it hasn't (this can happen if you have extremely long time constants), but again this is fairly rare. Of course, one should always check that the results look reasonable.

Limit cycle behavior is one reason pss convergence may lead to an accurate picture of phase-locked loop performance. The limit cycle frequency can be totally asynchronous to the fundamental frequency and hence not captured accurately in the pss solution. Other parameters in data recovery loops such as baseline wander will also not necessarily be accurately captured in a pss solution. Hence, my personal thought is that after a set of transient simulations validate desired operation, perhaps a pss based solution might be explored. It would not be my initial choice for PLL validation.

Shawn