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PSS for PLL loop

I am runnnig PSS for PLL with VCO and divider being ideal. I see that PLL loop is converged in PSS. Loop bandwidth is 10MHz. When I give -100dBc noise in reference signal source to PFD, at the output of vco, I am seeing 1/s (integrator) behaviour even below the bandwidth of PLL. Ideally, within the bandwidth , there should be flat noise from reference source. I turned off all noises except reference voltage source. How to interpret this behaviour at VCO noise?

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HatemAdly over 2 years ago

how did you build an ideal divider? The PSS analysis didn't work with the Verilog-A divider code due to what is called hidden states.
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Andrew Beckett over 2 years ago in reply to HatemAdly

See the RF models at https://designers-guide.org/verilog-ams/index.html for an example.

Andrew
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Andrew Beckett over 2 years ago in reply to HatemAdly

See the RF models at https://designers-guide.org/verilog-ams/index.html for an example.

Andrew
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