i want to read (2 dimensional array) , not only the first line

The other question that i want to ask about why most of the read files must be with extension .csv and not txt file ?  

It's not clear what you want here. Your code only reads one line here because it only calls $fscanf once in the initial_step block. It reads three values from the first line, but when you say:

Hagar Hendy said:

the first line will be on port A, second line on: port b , third line on: port C

I don't know what you mean - you have three values, and so how are these three values on each line going to "be on" port a,b,c respectively (for each line)?

Hagar Hendy said:

The other question that i want to ask about why most of the read files must be with extension .csv and not txt file ?  

The file can have whatever suffix you like - there's nothing to say that it has to be called ".csv" - it would equally well work with a "txt" file. The suffix of the file doesn't matter here.

Andrew

i want to represent it as pulses on each port ,here is my editing to the code 

// VerilogA for my_library, read_file, veriloga

`include "constants.vams"
`include "disciplines.vams"

module read_file (a,b,c,clkin);
output a,b,c;
electrical a,b,c,clkin;
integer in_file_0,data_value, valid,count_0,count_1,count_2,retval;
real A,B,C,v0_int,v1_int,v2_int,vthreshold;
real trise,tdelay,tfall;
// real int_value,v0_int,int_valu;

analog begin
@(initial_step) begin
in_file_0 = $fopen("/home/hh1667/ee610/my_library/read_file/data2.txt","r");
// while (retval <4) begin
retval =($fscanf (in_file_0, "%f,%f,%f", A,B,C));
count_0= A;
$display("%f", A);
count_1 =B;
$display("%f", B);
count_2 =C;
$display("%f", C);
// retval =retval+1;
// end
//$display("%f,%f,%f", A,B,C);
v0_int = A;
v1_int = B;
v2_int = C;

end
//@ (cross(V(clkin)-vthreshold, +1)) begin
//vthreshold = 0.5;
//trise = 1e-12;
//tfall = 1e-12;
//while (retval ==3) begin
//retval =($fscanf (in_file_0, "%f,%f,%f", A,B,C));
//count_0= A;
//count_1 =B;
// count_2 =C;
//end
// end
//V(a) <+transition(A, tdelay, trise, tfall);
//V(b) <+transition(B, tdelay, trise, tfall);
//V(c) <+transition(C, tdelay, trise, tfall);
//$display("%f", A);
//$fclose( in_file_0 );
end

endmodule

This will do what you want (I think, from your description):

// VerilogA for my_library, read_file, veriloga

`include "constants.vams"
`include "disciplines.vams"

module read_file (a,b,c,clkin);
output a,b,c;
electrical a,b,c,clkin;
integer in_file_0,data_value, valid,count_0,count_1,count_2,retval;
integer index;
parameter real vthreshold=0.5;
parameter real trise=1e-12;
parameter real tfall=1e-12;
parameter real tdelay=1e-12;

parameter integer numLines=3;
real A[numLines-1:0],B[numLines-1:0],C[numLines-1:0];
real Aint,Bint,Cint;

analog begin
  @(initial_step) begin
    in_file_0 = $fopen("/home/hh1667/ee610/my_library/read_file/data2.txt","r");
    retval =($fscanf (in_file_0, "%f,%f,%f", A[0],A[1],A[2]));
    retval =($fscanf (in_file_0, "%f,%f,%f", B[0],B[1],B[2]));
    retval =($fscanf (in_file_0, "%f,%f,%f", C[0],C[1],C[2]));
    index=0;

  end
  @ (cross(V(clkin)-vthreshold, +1)) begin
    Aint=A[index];
    Bint=B[index];
    Cint=C[index];
    if (index<numLines-1) index++;
  end
  V(a) <+transition(Aint, tdelay, trise, tfall); 
  V(b) <+transition(Bint, tdelay, trise, tfall); 
  V(c) <+transition(Cint, tdelay, trise, tfall);
end

endmodule

Andrew Beckett said:

/ VerilogA for my_library, read_file, veriloga `in

when i wrote the code, it is highlighted here that there is syntax error, as shown in red , the "end "that below  for "if" and not for "@cross(V(clkin)-vthreshold,+1))" is that correct ?

The if does not need an end because there's no begin in the body of the if statement. You only need begin/end pairs if you have multiple statements, and the index++ is a single statement.

I do not get this error if I use the code I posted in the VerilogA editor in Virtuoso. So I have a few questions:

1. What do you get in View→Parser Log File? This should contain any errors
2. Specifically what error do you have when you move your cursor over the red marked regions - you should have a tool tip showing the error (maybe it's just "syntax error"?). Is it the same over both of the red regions?
3. Which Spectre version are you using? This should appear in the spectre.out log file from simulation (near the top) or by typing "spectre -W" in the UNIX terminal
4. Which IC sub-version are you using? Type getVersion(t) in the CIW to retrieve this.

Andrew

1- this is the error as shown in the 2 screenshots:

the version in the below comment 

1- this is the error as shown in the 2 screenshots:

the version in the below comment 

here spectre version 

OK, so you're using an old Spectre version (from 6 years ago), and also an old IC version.

It seems that the Spectre Verilog-A parser handles this code from a SPECTRE19.1 version (I tried with the latest ISR for SPECTRE19.1 and it was OK).

The issue is with the index++. If you change that part of the code to index=index+1; then it will pass even in the version you're using.

You might want to consider using a newer version; we've had 5 major versions of Spectre since the version you're using.

Regards,

Andrew

now, i am able to create a symbol , but when i run the simulation this error shown as below :

also i am  student, and i am using this version through my institute, so i don't know how to use the newest version, or i think i have to let my advisors know that version that i am using is old. 

My guess is that your data2.txt file has Windows line endings. Can you show the output of:

cat -vet /home/hh1667/ee610/my_library/read_file/data2.txt

(in a UNIX terminal window)?

My guess that the solution is to run:

dos2unix /home/hh1667/ee610/my_library/read_file/data2.txt

to convert the line endings and it should then work. I tested the file with Windows (DOS) line endings, and it failed with the same error that you saw (with SPECTRE16.1). With newer Spectre versions, it worked fine even with the Windows line endings.

Regards,

Andrew

t:

yeah, it works thanks a lot for your help, appreciate your support