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sah like functionality required

engg987

Hi There,

I want to implement a block using verilogA which can sample input analog voltage at very first edge of the clock and and retain if forever. sah does similar functioanlity but it updates output at every positive edge of clock.

Thank you

  • `include "discipline.h"
`include "constants.h"

//--------------------
// sah_first (modified from sah_ideal in ahdlLib)
//
// -  ideal sample and hold amplifier
//
// vin:		[V,A]
// vclk:	[V,A]
// vout:	[V,A]
//
// INSTANCE parameters
//    vtrans_clk = transition voltage of the clock [V]
//   
// MODEL parameters
//    {none}
//
module sah_first(vin, vout, vclk);
input vin, vclk;
output vout;
electrical vin, vout, vclk;
parameter real vtrans_clk = 2.5;
integer count;
real vout_val;

	analog begin
		@ (cross(V(vclk) - vtrans_clk, 1.0))
		    if (count<1) begin
			vout_val = V(vin);
			count=count+1;
		    end
		V(vout) <+ vout_val ;
	end
endmodule

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