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How to extract the junction capacitor in pmos capacitor??

chjang

I am chung-ang university student, I have a problems when I extract parasitic component pmos cap in layout PEX.

This is physical structure of pmos cap, and that modeling schematic.

When I run PEX in Layout, I think Cch_nw, and Cnw_ps (parasitic capaciors) aren't extracted, because when i extend N-Well layer (= I think Cnw_ps should be increased due to junction area increasing ), there is no change of PEX result.

Please let me know, How to I extract the junction capacitor like Cch_nw, and Cnw_ps in the Layout??

  • Hi chung-ang,

    if Cch_nw is related to charges in the channel region, then it is normally covered by your SPICE model. The p+-SD/NW junction capacitance is represented by extracted area/Perimeter of the p+ regions. NW/psub junction capacitance can extracted in a similar way. This depends on whether your extraction deck recognizes such parasitic diode, and your SPICE models include such a diode.

    Guangjun

  • in reply to Guangjun Cao

    Firstly, thank you to reply my question.

    In my case, The Transitors (N/P mos) have junction capacitance represented by area/perimeter of p+ regions.

    But, NW/psub junction capacitance is not included, and the my extraction deck can't recognize parasitic diode.

    For example, when i use same size of pmos, and extend N-well layer to increase area/perimeter of NW/psub.

    And then, i extract the 2 type of layout about pmos cap, their extracted parasitic capacitance is exactly same.

    I think i should add the parasitic junction capacitance according to junction area depending on layout, and 

    value of capacitance density (F/m2) should be refer to my assigned PDK documentation. 

    What do you think of my opinion??

  • in reply to chjang

    If your PDK has SPICE model for such a diode, then all you need is to add the extraction code to extract the device/parameters, based on model requirements. Otherwise, you will have to create a model youself. Your PDK may already have a p+-NW diode as a primary device. in such case, your recognition layer for parasitic NW/PSUB diodes needs to be refined to avoid conflicts.

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