Global/Local Variables depending on different operation modes

Dear ayeyla,

ayayla said:

The problem is that this if statement(or case or ternary operations) can get easily complicated and difficult to maintain.

I am looking at how setting many dependent variables over different operation mode. I am wondering what the best way is to set these design variables.

I can understand your concern with difficulty in maintaining and sharing complex conditional expressions that define variable values. I don't know the details of what functions your dependent variables represent in your test bench (i.e., an initial condition for a node, voltage source value, simulation parameter, etc...). However, you did note:

ayayla said:

For each of these modes, I have different registers/look-up values. To make things easier, I have couple specific design variables(like "BW" below) which I use to change the other design variables.

Hence, perhaps the dependent variables are setting voltage source values that represent node voltages or current source values that provide current sources. What comes to mind to facilitate understanding, debugging, and changing the relationship between your independent variables (BW) and the resulting dependent variables is to create a verilog-A block with an input set the design variable BW and outputs varX, varY, varZ...varT.  Hence, each output will be represented by a verilog-A expression dependent on the value of input BW.

This does not eliminate conditional expressions, but takes advantage of verilog-A syntax and its code structure to ease your maintenance and enhance the sharing of the expressions to others who might use your test bench. As a example of what the code might look like, I have attached a simple verilog-A implementation of an 8-bit ADC.  A set of if expressions define the logical values for its 8 outputs. In your specific case, the signal "vin" might be a voltage source whose value if your independent variable "BW", and each output might be your dependent outputs varX, vary Y....

I won't claim this is an "optimal" solution! However, it came to mind as one way to ease your concerns with using ADE conditional expressions.

Shawn

// VerilogA for simple transient compatible eightbit_ad,
// sml 8/10/2020


`include "constants.vams"
`include "disciplines.vams"

module eightbit_ad(VOUT, VDD, VIN, VSS);
output [7:0] VOUT;
electrical [7:0] VOUT;
input VDD;
electrical VDD;
input VIN;
electrical VIN;
input VSS;
electrical VSS;
integer vin_integer;
parameter real rise_fall_time = 50e-12;
integer vout[7:0];

   analog begin
   
   vin_integer = V(VIN,VSS);

   if (vin_integer%256<128) V(VOUT[7],VSS)<+V(VSS);
      else V(VOUT[7],VSS)<+V(VDD,VSS);   
   V(VOUT[7],VSS)<+ transition(V(VDD)*vout[7],rise_fall_time,rise_fall_time);

   if (vin_integer%128<64) V(VOUT[6],VSS)<+V(VSS);
      else V(VOUT[6],VSS)<+V(VDD,VSS);   
   V(VOUT[6],VSS)<+ transition(V(VDD)*vout[6],rise_fall_time,rise_fall_time);

   if (vin_integer%64<32) V(VOUT[5],VSS)<+V(VSS);
      else V(VOUT[5],VSS)<+V(VDD,VSS);   
   V(VOUT[5],VSS)<+ transition(V(VDD)*vout[5],rise_fall_time,rise_fall_time);

   if (vin_integer%32<16) V(VOUT[4],VSS)<+V(VSS);
      else V(VOUT[4],VSS)<+V(VDD,VSS);   
   V(VOUT[4],VSS)<+ transition(V(VDD)*vout[4],rise_fall_time,rise_fall_time);
   
   if (vin_integer%16<8) V(VOUT[3],VSS)<+V(VSS);
      else V(VOUT[3],VSS)<+V(VDD,VSS);   
   V(VOUT[3],VSS)<+ transition(V(VDD)*vout[3],rise_fall_time,rise_fall_time);

   if (vin_integer%8<4) V(VOUT[2],VSS)<+V(VSS);
      else V(VOUT[2],VSS)<+V(VDD,VSS);   
   V(VOUT[2],VSS)<+ transition(V(VDD)*vout[2],rise_fall_time,rise_fall_time);

   if (vin_integer%4<2) vout[1]=0;
      else vout[1]=1;
   V(VOUT[1],VSS)<+ transition(V(VDD)*vout[1],rise_fall_time,rise_fall_time);

   if (vin_integer%2<1) vout[0]=0;
      else vout[0]=1;
   V(VOUT[0],VSS)<+ transition(V(VDD)*vout[0],rise_fall_time,rise_fall_time);
   
   end
   
endmodule

Dear ayeyla,

ayayla said:

The problem is that this if statement(or case or ternary operations) can get easily complicated and difficult to maintain.

I am looking at how setting many dependent variables over different operation mode. I am wondering what the best way is to set these design variables.

I can understand your concern with difficulty in maintaining and sharing complex conditional expressions that define variable values. I don't know the details of what functions your dependent variables represent in your test bench (i.e., an initial condition for a node, voltage source value, simulation parameter, etc...). However, you did note:

ayayla said:

For each of these modes, I have different registers/look-up values. To make things easier, I have couple specific design variables(like "BW" below) which I use to change the other design variables.

Hence, perhaps the dependent variables are setting voltage source values that represent node voltages or current source values that provide current sources. What comes to mind to facilitate understanding, debugging, and changing the relationship between your independent variables (BW) and the resulting dependent variables is to create a verilog-A block with an input set the design variable BW and outputs varX, varY, varZ...varT.  Hence, each output will be represented by a verilog-A expression dependent on the value of input BW.

This does not eliminate conditional expressions, but takes advantage of verilog-A syntax and its code structure to ease your maintenance and enhance the sharing of the expressions to others who might use your test bench. As a example of what the code might look like, I have attached a simple verilog-A implementation of an 8-bit ADC.  A set of if expressions define the logical values for its 8 outputs. In your specific case, the signal "vin" might be a voltage source whose value if your independent variable "BW", and each output might be your dependent outputs varX, vary Y....

I won't claim this is an "optimal" solution! However, it came to mind as one way to ease your concerns with using ADE conditional expressions.

Shawn

// VerilogA for simple transient compatible eightbit_ad,
// sml 8/10/2020


`include "constants.vams"
`include "disciplines.vams"

module eightbit_ad(VOUT, VDD, VIN, VSS);
output [7:0] VOUT;
electrical [7:0] VOUT;
input VDD;
electrical VDD;
input VIN;
electrical VIN;
input VSS;
electrical VSS;
integer vin_integer;
parameter real rise_fall_time = 50e-12;
integer vout[7:0];

   analog begin
   
   vin_integer = V(VIN,VSS);

   if (vin_integer%256<128) V(VOUT[7],VSS)<+V(VSS);
      else V(VOUT[7],VSS)<+V(VDD,VSS);   
   V(VOUT[7],VSS)<+ transition(V(VDD)*vout[7],rise_fall_time,rise_fall_time);

   if (vin_integer%128<64) V(VOUT[6],VSS)<+V(VSS);
      else V(VOUT[6],VSS)<+V(VDD,VSS);   
   V(VOUT[6],VSS)<+ transition(V(VDD)*vout[6],rise_fall_time,rise_fall_time);

   if (vin_integer%64<32) V(VOUT[5],VSS)<+V(VSS);
      else V(VOUT[5],VSS)<+V(VDD,VSS);   
   V(VOUT[5],VSS)<+ transition(V(VDD)*vout[5],rise_fall_time,rise_fall_time);

   if (vin_integer%32<16) V(VOUT[4],VSS)<+V(VSS);
      else V(VOUT[4],VSS)<+V(VDD,VSS);   
   V(VOUT[4],VSS)<+ transition(V(VDD)*vout[4],rise_fall_time,rise_fall_time);
   
   if (vin_integer%16<8) V(VOUT[3],VSS)<+V(VSS);
      else V(VOUT[3],VSS)<+V(VDD,VSS);   
   V(VOUT[3],VSS)<+ transition(V(VDD)*vout[3],rise_fall_time,rise_fall_time);

   if (vin_integer%8<4) V(VOUT[2],VSS)<+V(VSS);
      else V(VOUT[2],VSS)<+V(VDD,VSS);   
   V(VOUT[2],VSS)<+ transition(V(VDD)*vout[2],rise_fall_time,rise_fall_time);

   if (vin_integer%4<2) vout[1]=0;
      else vout[1]=1;
   V(VOUT[1],VSS)<+ transition(V(VDD)*vout[1],rise_fall_time,rise_fall_time);

   if (vin_integer%2<1) vout[0]=0;
      else vout[0]=1;
   V(VOUT[0],VSS)<+ transition(V(VDD)*vout[0],rise_fall_time,rise_fall_time);
   
   end
   
endmodule