Veriloga model of load behaves differently when standalone or instantiated with other circuit

Virtuoso version IC6.1.8-64b.500.27

Hi all,

I have the following behavioral model of a current load:

// VerilogA for library, icustom, veriloga

`include "constants.vams"
`include "disciplines.vams"

module icustom(iload);

output iload;
electrical iload;

ground gnd;

real _load_current_array[1:20] = '{1u,2u,4u,8u,10u,20u,40u,80u,100u,200u,400u,800u,1m,2m,4m,8m,10m,20m,40m,50m};
real _iload = 0;
genvar i;

analog begin
    @(initial_step) $strobe("module initialized");
    for (i=1; i<=20; i = i+1) begin
        @(timer(500u+i*50u)) begin
            _iload = _load_current_array[i];
            $strobe("current transition at %r", $abstime);
        end
    end

    I(iload,gnd) <+ transition(_iload, 10n, 10n, 10n);
end

endmodule

I created a standalone testbench to check its behavior and it works as expected. Then I instantiated within a real circuit (a the load of an LDO) and the behavior varies, as seen in the plot below:

Some of the transitions occur as expected but other happen at different times or with different rise times. I'm having a hard time understanding why the behavior would change and I don't see any clearly wrong in the model. Any pointers are highly appreciated.