Verilog-A: is it possible to nest analog events? e.g. timer() inside cross()?

Hi! I'm trying to recreate the behavior of an synchronous controller in Verilog-A. The real circuit is made of delays and logic, and basically creates a sequence of pulses after been triggered by the edge of an asynchronous clock.

So far:

1. I tried to implement this behavior using nested timers inside a crossing event for detecting the clock edges, but (despite compiling & simulating with no errors/warnings) this didn't work--se code & resulting waveforms (1) below.
2. I found a workaround that uses absdelay() to create delayed copies of the clock, and generates the desired outputs on the crossings of these delayed clocks--see code/waveforms (2) below. This solution seems inefficient when generating a large number of outputs, due to the added overhead... is this *the only* possible way to implement the desired behavior?

Can anybody please help me to understanding why (1) doesn't work and/or how to fix it?

Thanks and regards,
Jorge.

(1) This code doesn't work:

`include "discipline.h"
module examplePulseGenerator (CLK,OUT1,OUT2);
input  CLK;    voltage CLK;
output OUT1;   voltage OUT1;
output OUT2;   voltage OUT2;

parameter real    VSS       = 0;
parameter real    VDD       = 1;
parameter real    Tguard    = 20p;
parameter real    Tdelay1   = 50p;
parameter real    Twidth1   = 200p;
parameter real    Tdelay2   = 0;
parameter real    Twidth2   = 400p;

real Tstart1   = Tdelay1;
real Tstop1    = Tstart1+Twidth1;
real Tstart2   = Tstop1+Tguard+Tdelay2;
real Tstop2    = Tstart2+Twidth2;

real OUT1_unfiltered;
real OUT2_unfiltered;

analog begin

    @(initial_step) begin
        OUT1_unfiltered = VSS;
        OUT2_unfiltered = VSS;
    end

    @(cross(V(CLK)-0.5*(VDD+VSS),1)) begin
        @(timer($abstime+Tstart1)) OUT1_unfiltered = VDD;
        @(timer($abstime+Tstop1))  OUT1_unfiltered = VSS;
        @(timer($abstime+Tstart2)) OUT2_unfiltered = VDD;
        @(timer($abstime+Tstop2))  OUT2_unfiltered = VSS;
    end

    V(OUT1) <+ transition(OUT1_unfiltered,0,10p,10p);
    V(OUT2) <+ transition(OUT2_unfiltered,0,10p,10p);

end
endmodule

(2) This code works:

`include "discipline.h"
module examplePulseGenerator (CLK,OUT1,OUT2);
input  CLK;    voltage CLK;
output OUT1;   voltage OUT1;
output OUT2;   voltage OUT2;

parameter real    VSS       = 0;
parameter real    VDD       = 1;
parameter real    Tguard    = 20p;
parameter real    Tdelay1   = 50p;
parameter real    Twidth1   = 200p;
parameter real    Tdelay2   = 0;
parameter real    Twidth2   = 400p;

real Tstart1   = Tdelay1;
real Tstop1    = Tstart1+Twidth1;
real Tstart2   = Tstop1+Tguard+Tdelay2;
real Tstop2    = Tstart2+Twidth2;

real OUT1_unfiltered;
real OUT2_unfiltered;

real CLKdelayed_Tstart1;
real CLKdelayed_Tstop1;
real CLKdelayed_Tstart2;
real CLKdelayed_Tstop2;

analog begin

    @(initial_step) begin
        OUT1_unfiltered = VSS;
        OUT2_unfiltered = VSS;
    end

    CLKdelayed_Tstart1 = absdelay(V(CLK),Tstart1);
    CLKdelayed_Tstop1  = absdelay(V(CLK),Tstop1);
    CLKdelayed_Tstart2 = absdelay(V(CLK),Tstart2);
    CLKdelayed_Tstop2  = absdelay(V(CLK),Tstop2);

    @(cross(CLKdelayed_Tstart1 -0.5*(VDD+VSS),1)) OUT1_unfiltered = VDD;
    @(cross(CLKdelayed_Tstop1  -0.5*(VDD+VSS),1)) OUT1_unfiltered = VSS;
    @(cross(CLKdelayed_Tstart2 -0.5*(VDD+VSS),1)) OUT2_unfiltered = VDD;
    @(cross(CLKdelayed_Tstop2  -0.5*(VDD+VSS),1)) OUT2_unfiltered = VSS;

    V(OUT1) <+ transition(OUT1_unfiltered,0,10p,10p);
    V(OUT2) <+ transition(OUT2_unfiltered,0,10p,10p);

end
endmodule