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  3. Only a functional file was created after using generate...

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Only a functional file was created after using generate in Verilog

RuihW
RuihW over 2 years ago

Hi everyone,

I encountered a problem when importing Verilog in Cadence Virtuoso 6.1.8. I created an inverter (schematic and symbol) named "INV" using TSMC's 180nm package, and then I tried creating a simple network with 4 of them connected in parallel using Verilog.

module parallelINV (input A);

genvar i;

generate

     for(i=0;i<4;i=i+1) begin: connect_invs

        INV I(.A(A));

     end

endgenerate

endmodule

However, after importing the Verilog file, only a functional view and a symbol view were generated. But the most important one, the schematic view, was missing.

Then I removed the loop and hard coded all 4 instances. This time Cadence was able to create the schematic view.

module parallelINV (input A);

INV I0(.A(A));

INV I1(.A(A));

INV I2(.A(A));

INV I3(.A(A));

endmodule

How do I make the for loop work?

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  • Andrew Beckett
    Andrew Beckett over 2 years ago

    You can't. generate is seen as being a behavioural construct, and whilst the loop has constant parameters in this case, it still is evaluated during the elaboration step of the simulator rather than the compilation step that the Verilog import uses.

    Andrew

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  • RuihW
    RuihW over 2 years ago in reply to Andrew Beckett

    Thanks. In this case, is there any method to create multiple instances without hard coding every single one?

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  • Andrew Beckett
    Andrew Beckett over 2 years ago in reply to RuihW

    Not that I can think of. Other than writing a script to generate the expanded Verilog (that's what I'd do if there were a lot of instances).

    Andrew

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