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vbit pattern

JHC

instead of defining a vbit pattern in a ADE library .scs file can the pattern be generated in the ADE schematic or as a parameter which can be modified during simulation?

  • ShawnLogan

    Dear JHC,

    JHC said:
    or as a parameter which can be modified during simulation?

    If I understand correctly,  you would like a means to set the pattern as a design variable and then sweep the pattern design variable. If this is correct,  I'm not sure if you tried the methodology outlined at the On-line support site at URL:

    https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nX1CEAU&pageName=ArticleContent

    Shawn

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