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  3. How to include extracted output in your adexl simulation...

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How to include extracted output in your adexl simulation?

Vishesh Gupta
Vishesh Gupta over 2 years ago

Hi,

I have successfully generated spice output on quantus assura extraction and I got result in the form of .sp file. How do I include this extraction in my simulalations?

Regards,

Vishesh

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  • Andrew Beckett
    Andrew Beckett over 2 years ago

    Vishesh,

    I deleted your duplicate post in the feedback, suggestions and questions forum (which is not for technical questions).

    The best approaches are to either:

    1. Use an extracted view output (rather than SPICE output)
    2. Use a SmartView output (needs Quantus and Virtuoso from 2018 onwards)
    3. Use DSPF output

    If using either extracted or SmartView output, you'd pick the view to use in the hierarchy editor, or alter the view list in Setup->Environment in ADE to pick the view name first.

    If using DSPF, then use Setup->Simulation Files and specify the DSPF file to include - that should replace that block with the DSPF.

    Using SPICE is more complex and there's little benefit in doing so (you need to start worrying about getting terminal orders correct).

    Andrew

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  • Vishesh Gupta
    Vishesh Gupta over 2 years ago in reply to Andrew Beckett

    Hi Andrew,

    Thanks a lot for the reply!

    Just want to confirm one thing, is the output as "SPICE" exactly same as that of output as "Extracted view". In other words, can I use the "SPICE" file table of resistance and capacitance parasitics values to refer to the "av_extracted " drawn resistance and capacitance parasitics?

    I want to analyze my circuit parasitics and in the "av_extracted" view it is difficult to keep on zooming at various places . Or is there any way to generate a netlist file in the av_extracted view? Is there any way I can probe to a certain net or if I can get all the parasitics connected to a certain net ? 

    Thanks and Regards,

    Vishesh

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  • Andrew Beckett
    Andrew Beckett over 2 years ago in reply to Vishesh Gupta

    Generally speaking, foundries support (i.e. test) extracted view output (and smart view too); they don't necessarily test the SPICE output, and there is a possibility that designed device parameters may not be mapped correctly with SPICE (should be OK, but if it's not tested, there's a chance it's not right).

    The parasitics are supposed to be the same (after all, the extraction was the same). With SmartView you'd end up with a DSPF file netlisted, and with extracted view you'd end up with a spectre subckt netlist. Anyway, some good details on parasitic probing and the features of smart view can be found in this rapid adoption kit: Using Quantus Smart View in the Virtuoso Analog Design Environment (the parasitic reporting would work with Extracted View too).

    Andrew

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  • Vishesh Gupta
    Vishesh Gupta over 2 years ago in reply to Andrew Beckett

    Hi Andrew,

    Thanks a lot for the reply.

    Where can I find the "spectre subckt netlist" file mentioned above? Is there any default name to the file? What is the extension of the file?

    I am not able to access the link to the rapid adoption kit (it asks for "Cadence License Server Host Id" which I don't have). Do you have something else I can refer to?

    Thanks and Regards,

    Vishesh

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  • Andrew Beckett
    Andrew Beckett over 2 years ago in reply to Vishesh Gupta

    The netlist is produced when you simulate the design using ADE which incorporates an extracted view or smart view. You can also use Simulation→Netlist→Create to get it (from within ADE).

    Vishesh - you should contact whoever is the admin for your software setup to find out the host id.

    Anyway, you can simply get to the documentation by using any Help menu in Virtuoso and in the box at the top type "Smart View" - you'll get to relevant topics.

    Andrew

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  • Vishesh Gupta
    Vishesh Gupta over 2 years ago in reply to Andrew Beckett

    Hi Andrew,

    Thanks a lot for the reply.

    This solves my question.

    Regards,

    Vishesh

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