DC Convergence issues with custom device model

Hello, 

I am trying to simulate a circuit with newly developed custom device model but am facing DC convergence issues which I have not been able to resolve with the available online resource on the support website so far. 

I am using IC-618 & Spectre-211 (Version 21.1.0.303.isr5 64bit) in ++APS mode in a schematic with just 2 devices a couple of DC voltage sources.

Below are some of the messages from output log so any suggestions on how to diagnose the model specific issues will be very helpful.

~~~~~~~~~~~~~~~~~~~~~~~
Post-Simulation Summary
~~~~~~~~~~~~~~~~~~~~~~~
Analysis Analysis ID CPU (s) Elapsed (s)
1 info checkNPN_asserts 2.01e-03 2.62e-03
2 dc dcOp 2.08e-02 2.14e-02
3 info dcOpInfo 1.55e-03 2.06e-03
4 info modelParameter 1.23e-03 1.70e-03
5 info element 4.15e-03 4.87e-03
6 info outputParameter 1.25e-03 2.09e-03
7 info designParamVals 1.00e-02 1.11e-02
8 info primitives 6.77e-04 1.66e-03
9 info subckts 1.66e-03 2.52e-03
------------------------------------------------------------------------------------
Total 4.33e-02 5.00e-02
Average 4.82e-03 5.56e-03
Elapsed Min info primitives 6.77e-04 1.66e-03
Elapsed Max dc dcOp 2.08e-02 2.14e-02

~~~~~~~~~~~~~~~~~~~~~~~

Error found by spectre during DC analysis `dcOp'.
ERROR (SPECTRE-16385): There were 13 attempts to find the DC solution. In some of those attempts, a signal exceeded the blowup limit of its quantity. The last signal that failed is V(I26.BETA) = -1.15146 GV, for which the quantity is `V' and the blowup limit is (1 GV). It is possible that the circuit has no DC solution. If you really want signals this large, set the `blowup' parameter of this quantity to a larger value.
ERROR (SPECTRE-16080): Cannot print DC solution because DC did not converge. Resolve the convergence issue and rerun the simulation.

thanks

Dear sidm,

sidm said:

I am trying to simulate a circuit with newly developed custom device model but am facing DC convergence issues

For me anyway, your post really does not provide sufficient information to provide any specific guidance. An input netlist (input.scs) that shows our schematic and the details of your analysis command (i.e.., what analysis options you are choosing) would be helpful. In addition, please include the log file and something more of a description other than "custom model" of your model.

Obviously, if you are generating your own model, I'm not sure how you verified that a DC solution does exist for the operating conditions of your circuit. If you wanted to verify that it is not the basic circuit in which your models are placed nor the basic simulator, you might consider replacing your custom model with an "ideal" model available from the Cadence library (for example, an nmos or pmos device) and determine if your simulation completes successfully.

Without more basic information on your simulation setup, model, and results, I, for one, cannot really add any more specific debugging suggestions - sorry sidm!

Shawn

I combined your (sidm's) two posts - one had been stuck in moderation briefly, probably because of the repeated text.

Anyway, Shawn is right, there's not enough to go on here. The best bet is to contact customer support, but failing that you might get lucky (if somebody has time here to answer) if you can provide the input netlist, any veriloga models (if your "custom model" is Verilog-A) and enough to run the simulation which fails to converge.

Andrew

Thanks for the reply and sorry for the double posting as my first post seems was blocked as spam or something hence I created a second one with lesser output log file content. 

I am trying to check if I can share the model file. 

In the meantime can you please let me know if the custom model simulated in Pspice can it still fail when simulating in Spectre ?

regards

Yes, this can happen. Without knowing the details though, it's hard to know if that's reasonable or not (sometimes you can find that there may be some heuristics on one simulator or other to deal with poor models that handle them better in one simulator than the other).

Andrew