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Query hierarchical Spectre model for used subckt

Greetings,

The Problem:

I am using Spectre model library which consist of certain base models, which depending on design variable or model parameter can include a supplementary subckt. These models can either include the extra subckts directly in the model files hierarchy or on netlist level. I'd like to be able understand whether the particular model used in a given netlist, actually leverages that supplementary subckt

The clue:

Adding the following analysis in my netlist subckts info what=subckts where=rawfile, produces a subckts.info.subckts file in psf directory, that has information about all subckt used in my netlist after expanding the models. This list is flat, meaning it has no information about in which "parent" was this subckt used in. In my netlist directory, I also have the .includedModels which stores list of all top level models used in my input.scs file. I need a way to map the subckts from subckts.info.subckts back to models in my .includedModels / input.scs, so that I can confidently state: "Okay, modelA.scs doesn't actually use supplementaryModel.scs"

Where am I at:

Initially, I thought I could just brute force the problem, by having all the subckts from subcksts.info.subckts and text-parse all the models from the library to try to establish the relation between that subckt and the top level model. However, this is A) slow and painful and B) impossible if model files are encrypted. I am thinking if Spectre is able to spit this information for me in some way, after all it obviously does go through the process of model expansion in forward direction, it might be possible to store the relations in the process.

*I quite frivolously used the terms model and subckt and in this particular case I've used them somewhat interchangeably.

Any suggestions are highly appreciated. Thank you!

Andrew Beckett over 2 years ago

Boris,

The output from the subckts info analysis (which might be easier to look at if you change the output on the Outputs→Save All form to be "file" rather than "rawfile" - this will give you a text file in the netlist directory - you can also specify the name to avoid it being called input.info.subckts) does contain information about each subckt and when the names of the hierarchical instances which instantiate that subckt. For example:

Sub-Circuit: gpdk090_nmos2v
Subckt Params: geo_fac mm_dl ad mm_mu0 nrs as mm_delvt mm_dtox pd w mm_dw ps
        varvt l simM nrd
Subckt Terminals: D G S B
Subckt Instances: NM0 I30.NM11 I30.NM5 I30.NM4 I30.NM3 I30.NM2 I30.NM1 I30.NM0
        I30.I23.NM3 I30.I23.NM2 I30.I22.NM3 I30.I22.NM2 I30.I21.NM1 I30.I21.NM0
        I30.I20.NM1 I30.I20.NM0 I28.NM11 I28.NM5 I28.NM4 I28.NM3 I28.NM2
        I28.NM1 I28.NM0 I28.I23.NM3 I28.I23.NM2 I28.I22.NM3 I28.I22.NM2
        I28.I21.NM1 I28.I21.NM0 I28.I20.NM1 I28.I20.NM0 ADC_INTERP_ARRAY.NM2
        ADC_INTERP_ARRAY.NM6 ADC_INTERP_ARRAY.NM7 ADC_INTERP_ARRAY.NM5
        ADC_INTERP_ARRAY.I1.NM2 ADC_INTERP_ARRAY.I1.NM0 ADC_INTERP_ARRAY.I1.NM1
        ADC_INTERP_ARRAY.I1.NM3 ADC_INTERP_ARRAY.I1.NM4 ADC_INTERP_ARRAY.I1.NM5
        ADC_INTERP_ARRAY.I2.NM2 ADC_INTERP_ARRAY.I2.NM0 ADC_INTERP_ARRAY.I2.NM1
        ADC_INTERP_ARRAY.I2.NM3 ADC_INTERP_ARRAY.I2.NM4 ADC_INTERP_ARRAY.I2.NM5
        ADC_INTERP_ARRAY.I3.NM2 ADC_INTERP_ARRAY.I3.NM0 ADC_INTERP_ARRAY.I3.NM1
        ADC_INTERP_ARRAY.I3.NM3 ADC_INTERP_ARRAY.I3.NM4 ADC_INTERP_ARRAY.I3.NM5
        ADC_INTERP_ARRAY.I4.NM2 ADC_INTERP_ARRAY.I4.NM0 ADC_INTERP_ARRAY.I4.NM1
        ADC_INTERP_ARRAY.I4.NM3 ADC_INTERP_ARRAY.I4.NM4 ADC_INTERP_ARRAY.I4.NM5
        ADC_INTERP_ARRAY.I5.NM2 ADC_INTERP_ARRAY.I5.NM0 ADC_INTERP_ARRAY.I5.NM1
        ADC_INTERP_ARRAY.I5.NM3 ADC_INTERP_ARRAY.I5.NM4 ADC_INTERP_ARRAY.I5.NM5
        ADC_INTERP_ARRAY.I6.NM2 ADC_INTERP_ARRAY.I6.NM0 ADC_INTERP_ARRAY.I6.NM1
        ADC_INTERP_ARRAY.I6.NM3 ADC_INTERP_ARRAY.I6.NM4 ADC_INTERP_ARRAY.I6.NM5
        ADC_INTERP_ARRAY.I7.NM2 ADC_INTERP_ARRAY.I7.NM0 ADC_INTERP_ARRAY.I7.NM1
        ADC_INTERP_ARRAY.I7.NM3 ADC_INTERP_ARRAY.I7.NM4 ADC_INTERP_ARRAY.I7.NM5
        ADC_INTERP_ARRAY.I8.NM2 ADC_INTERP_ARRAY.I8.NM0 ADC_INTERP_ARRAY.I8.NM1
        ADC_INTERP_ARRAY.I8.NM3 ADC_INTERP_ARRAY.I8.NM4 ADC_INTERP_ARRAY.I8.NM5
        ADC_INTERP_ARRAY.I9.NM2 ADC_INTERP_ARRAY.I9.NM0 ADC_INTERP_ARRAY.I9.NM1
        ADC_INTERP_ARRAY.I9.NM3 ADC_INTERP_ARRAY.I9.NM4 ADC_INTERP_ARRAY.I9.NM5
        ADC_INTERP_ARRAY.I10.NM2 ADC_INTERP_ARRAY.I10.NM0
        ADC_INTERP_ARRAY.I10.NM1 ADC_INTERP_ARRAY.I10.NM3
        ADC_INTERP_ARRAY.I10.NM4 ADC_INTERP_ARRAY.I10.NM5
        ADC_INTERP_ARRAY.I11.NM2 ADC_INTERP_ARRAY.I11.NM0
        ADC_INTERP_ARRAY.I11.NM1 ADC_INTERP_ARRAY.I11.NM3
        ADC_INTERP_ARRAY.I11.NM4 ADC_INTERP_ARRAY.I11.NM5 ADC_REF_LADDER.M0
        ADC_REF_LADDER.ADC_CASCODE_OPAMP.NM10
        ADC_REF_LADDER.ADC_CASCODE_OPAMP.NM12
        ADC_REF_LADDER.ADC_CASCODE_OPAMP.NM9
        ADC_REF_LADDER.ADC_CASCODE_OPAMP.NM14

(this was a truncated output).

It sounds as if you don't want the instance name, but the name of the subckt that (say) ADC_REF_LADDER.ADC_CASCODE_OPAMP.NM14 is contained within. You could find that in the same file:

Sub-Circuit: adc_cascode_opamp
Subckt Params: 
Subckt Terminals: OUT VSS VDD INN INP IREF SIDDQ
Subckt Instances: ADC_REF_LADDER.ADC_CASCODE_OPAMP

and so on. Probably a bit of python/perl to process the text file wouldn't be too hard.

I don't think there's anything that directly says the subckt names each subckt is instantiated within.

Regards,

Andrew

BorisD over 2 years ago in reply to Andrew Beckett
Hello Andrew,

Thank you for your replay.

You are correct, however I was running into a corner case. This has to do with the model topology itself. Here is the basic structure of one such model that doesn't show up with its hierarchy in the subckt info analysis:

// myModels.lib.scs
section my_top_level_model_subckt
inline subckt my_top_level_model (t1 t2)
parameters
...
if ( design variable =! 0) {
instance (t2 t1) model_in_question ...
}
include "./base_my_top_level_model.scs"
my_top_level_model (t3 t4) my_top_level_model ...
ends my_top_level_model
endsection my_top_level_model_subckt

The subck info analysis shows this:

// xxx.info.subckt
Sub-Circuit: model_in_question
Subckt Params: ...
Subckt Terminals: t1 t2
Subckt Instances: <empty>

Sub-Circuit: my_top_level_model
Subckt Params: ...
Subckt Terminals: t1 t2
Subckt Instances: I0

It appears that if design_variable is not defined or condition is not met, the model_in_question subckt shows up in info file, but instance section remains empty. Which makes sense, now that I think about it, since these subckt are never used in this case. Anyways, from here, as Andrew said, it should be a matter of some scripting to achieve my initial goal.

Thanks again!
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