Unexpected capacitor values in the av_extracted view file output?

Vishesh.

Most likely the LVS rule deck is just extracting the w and l of the mos capacitor (the values look right), and there's nothing to derive the capacitance value. I don't know the details of your PDK, but maybe it only netlists the w and l for simulation and the capacitance is computed in the model (I would expect that the capacitance on the schematic is a visual aid to help you define the dimensions of the transistor used).

You should check with the PDK provider.

Andrew

Hi Andrew,

Thanks a lot for your reply!

Andrew Beckett said:

. I don't know the details of your PDK, but maybe it only netlists the w and l for simulation and the capacitance is computed in the model

I ran the simulation with different values of the capacitors and I got different values in the graph. So, I can conclude that it netlists the w and l for simulation?

I am really sorry but I don't understand why the capacitance is computed in the model and it doesn't reflect in the extracted view?

Is there any other way I can know the value of the mos cap after extraction? In general, I also want to confirm if the value of the mos capacitor should change after extraction?

Thanks a lot for your valuable time.

Vishesh

Vishesh Gupta said:

I am really sorry but I don't understand why the capacitance is computed in the model and it doesn't reflect in the extracted view?

With the caveat that I don't know the details of the PDK you're using, my assumption is that this nmos capacitor is just a shorted transistor. So the best way to model it is actually as a transistor - the capacitance comes from the dimensions of the device. The LVS tool extracts those dimensions (and additional areas potentially) and then you'll get the w and l and potentially other parameters which end up being netlisted for spectre. The parameter extraction in LVS doesn't need to compute any capacitance, because the simulation model will convert the w and l etc into the effective capacitance produced by that transistor.

On the schematic, there's probably a callback on the component that when you alter the w and l, it computes and displays what the expected capacitance would be - this is then an aid for you as a designer.

Vishesh Gupta said:

Is there any other way I can know the value of the mos cap after extraction? In general, I also want to confirm if the value of the mos capacitor should change after extraction?

As I said before, you'd have to ask the PDK provider. However, given that the w and l on the extracted device match the schematic, I would expect the capacitance to match the schematic too (to whatever level the capacitance number produced by the callbacks is accurate). Given that the mos capacitor is not a parasitic - the only things that would affect it are if some of the other dimensions on the device don't match the pre-layout assumptions. For example, this happens with MOS transistors, since whilst the w and l may match, the source and drains may be shared or extended altering the area and perimeter of the layout transistor, which would impact the capacitances associated with the source and drain; the LVS tool would extract these dimensions and then the simulation model would take those altered dimensions and that would affect the modelled capacitances around the transistor. Similar things may be happening with a moscap - but I don't know how much variation of the actual layout dimensions there could be with this device. As I said before, Quantus is not involved here - it's the LVS tool that is doing the measurements because it's not interconnect parasitics that are relevant here.

Regards,

Andrew

Hi Andrew,

Thanks a lot for the reply. Great Explanation!

All the parameters on which capacitance of the device depends (basically the equation for the model), is there any option with which I can access it in virtuoso? or do I have to contact the PDK provider for that?

Thanks and Regards,

Vishesh

Vishesh,

It's probably largely the gate capacitance of the transistor, but you'd have to speak to the foundry. Maybe it's in the PDK documentation or some other documentation about the process.

Andrew

Vishesh,

It's probably largely the gate capacitance of the transistor, but you'd have to speak to the foundry. Maybe it's in the PDK documentation or some other documentation about the process.

Andrew

Hi Andrew,

Thanks a lot! That answers my question.

Regards,

Vishesh