Set DC sources voltage from csv file

You could have a variable name as the DC value on each source and then load the design variables (over the Design Variables header in ADE use Right Mouse->Import from CSV).

Andrew

Thanks Andrew.

Where can I find the "Import from CSV" option? I checked both ADE L and ADE GXL but couldn't find it. I right-clicked on the design variables but didn't see the option.

Dear Ruihw,

RuihW said:

Where can I find the "Import from CSV" option? I checked both ADE L and ADE GXL but couldn't find it. I right-clicked on the design variables but didn't see the option.

You did not indicate what version of the tools you are using and if you using Assembler. If you are using ADE-L, you should seriously consider migrating to Assembler/Explorer as ADE-L is no longer supported. ADE-L does not support this feature.

There is a video that details how one may import and export design variables in Assembler at URL:

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V000007MdIXUA0&pageName=ArticleContent

Shawn

Thanks Shawn! This answers my question.

Dear RuihW.

RuihW said:

This answers my question.

Excellent! I am happy to read you are able to use a comma-separated variable file now to import your 100 design variables and are on your way! Thank you for letting us know too!

As a side note, if the relationship between the voltage source number and its value is known (or is a random variable), a shell script might be a candidate to create your comma-separated variable file. I've assembled an example that produces N values of a design variable with a base name of "source" who value is a random value centered about 0.50 V. The script is attached. I had to change the extension to ".txt" to upload it to the forum. To use it, issue the command:

$ mv create_des_var_csv_file.txt create_des_var_csv_file.scr

$ chmod +x create_des_var_csv_file.scr

The script and example follow.

Shawn

$ 

$ create_des_var_csv_file.scr vdc_source 10 variables.csv

Done! Output filename is "variables.csv".

$ cat variables.csv

Type,Name,Value,Enabled

variable,vdc_source0,.4533,enabled

variable,vdc_source1,.5074,enabled

variable,vdc_source2,.4616,enabled

variable,vdc_source3,.5157,enabled

variable,vdc_source4,.4699,enabled

variable,vdc_source5,.5240,enabled

variable,vdc_source6,.4782,enabled

variable,vdc_source7,.5323,enabled

variable,vdc_source8,.4866,enabled

$

#! /bin/bash
if [ $# -ne 3 ]; then
   echo "Usage: create_des_var_csv_file <base_design_variable_name> <number_of_design_variables_to_create> <output_file_name>"
   exit 127
fi

echo "Type,Name,Value,Enabled" > $3
number_of_design_variables_to_create_minus_1=`expr $2 - 1 | bc`

for i in $(seq 0 ${number_of_design_variables_to_create_minus_1});
do
	if [[ $i -lt ${number_of_design_variables_to_create_minus_1} ]]
	then
		value_of_design_variable=`expr "scale=4; 0.50 + 0.1*(($RANDOM - 16384)/32767)" | bc`
		echo "variable,$1$i,${value_of_design_variable},enabled" >> $3;
	fi
done
echo "Done! Output filename is \"$3\"."

Thanks for the info.

I do have another question: how can I programmatically set the design variable for each source in the schematic? Using your script as an example, how to set the corresponding dc value in the schematic as "vdc_source0", "vdc_source1" and up to "vdc_source99"?

I created the 100 sources using Verilog:

VDCSIM V0(.PLUS(Vout0), .MINUS(gnd));
VDCSIM V1(.PLUS(Vout1), .MINUS(gnd));
...

VDCSIM V99(.PLUS(Vout99), .MINUS(gnd));

But the code above only connects the + and - terminals, it doesn't set the DC voltage of the source. VDCSIM is same as the vdc model from the analogLib. I copied it to my own library and renamed it to VDCSIM.

You could use the approach I shared in this recent post. You'd need to change the code to either set inst~>vdc (rather than inst~>fileName) and work on vdc rather than vsource, and in the CCFincrVar change the cdfgData~>fileName to cdfgData~>vdc - but other than that the principle remains the same.

For your Verilog-based approach, not sure why you copied vdc to VDCSIM in your library (this should not be necessary if you have analogLib as a reference library - not sure how you're using this Verilog). Are you importing this Verilog to create a schematic or are you using the Verilog as-is?

Andrew

Thanks Andrew. I never used SKILL before so it took me a while to figure it out. Your method achieves what I need!

For the verilog code, I changed it back to call vdc instead of VDCSIM and this time it works. It was trying to create the schematic under analogLib, which I don't have write permission. That's why I copied it to my own library. It was likely a configuration issue.