Verilog A issue

Hello,

I'm currently working on modeling a basic/symmetrical charge pump in Verilog-A for the z domain. However, I'm encountering a discrepancy between the results obtained from the Verilog-A model and the schematic. I would like the Verilog-A model to closely resemble the behavior of the schematic model, particularly with respect to the steps observed in the output.

If anyone has experience with this issue or knows how to achieve the desired behavior in the Verilog-A model, I would greatly appreciate your assistance. Thank you in advance for your help!