• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. Generating an input signal which changes frequency at a...

Stats

  • Locked Locked
  • Replies 2
  • Subscribers 126
  • Views 5585
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Generating an input signal which changes frequency at a given rate

DenisJos
DenisJos over 2 years ago

Hi,

Is there a way to generate an input voltage stimuli which works at a certain frequency freq1 and after time t ramps to freq2 with a given rate of change like 150MHz/5ns.

Thanks,

DJ

  • Cancel
  • ShawnLogan
    ShawnLogan over 2 years ago

    Dear DenisJos,

    DenisJos said:
    Is there a way to generate an input voltage stimuli which works at a certain frequency freq1 and after time t ramps to freq2 with a given rate of change like 150MHz/5ns.

    I would consider using a verilog-A block with an input that allows you to change the frequency. There is an example of some code that Ken Kundert assembled in response to a question that you might use. In this fashion, you can set the frequency input to a value corresponding to freq1 until time t and then change it using a ramp to an input corresponding to freq2 at a rate corresponding to 150 MHz/5 ns.

    The relevant code from Mr. Kundert is at

    designers-guide.org/forum/YaBB.pl?num=1642147821

    and shown below for your convenience.

        module sinegen(out, freq, ampl, phase, offset);
        output electrical out;
        input wreal freq, ampl, phase, offset;
        parameter tt=1u from [0:inf);
        reg break = 0;
    
        always @(freq or ampl or phase or offset) break <= !break;
    
        analog begin
    	  @(posedge break or negedge break)
    		;
    	  V(out) <+ transition(ampl, 0, tt)*sin(transition(freq, 0, tt)*$abstime + transition(phase, 0, tt)) + transition(offset, 0, tt);
    	  $bound_step(10/freq);
        endmodule

    Shawn

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Andrew Beckett
    Andrew Beckett over 2 years ago in reply to ShawnLogan

    I had thought of an even simpler idea (just been busy yesterday and today and so didn't have a chance to post it). Use a Verilog-A model of a VCO (e.g. the "vco" component from ahdlLib) and then have a PWL voltage source setting the initial input frequency and then ramp up at the rate you want to the second frequency. That way you don't need anything other than the existing VCO model and a standard PWL voltage source.

    Regards,

    Andrew

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information