How to let VSR or ride to route all term(S/D) not just one Source or Drain ?

'Finish Wire' will complete the route to the single terminal highlighted by the flightline.

The are a number of options to auto route the complete net...

Navigator: Select net -> RMB -> Route With WA Overrides/Default Lookup (i.e. Use overrides in Wire Assistant or Default constraints)

Select net (in Navigator): Wire Assistant -> 'Automatic Routing' field -> Selected.

Dependant on the desired result consider RMB -> Finish Trunk (recommended).

See support.cadence.com/COSAgreementPage?artId=a1O0V000006De3JUAS&caseSessionKey=null&id=0690V000004fQoHQAU&sq=null or docs for more detail.

Hi RobMan ,

This device has a guardring and S/D ,

I use the Navigator and click the net , the flightline show opens(2) , one is guardring , 2 term on S/D (now it show left side term)

then Route with WA Overwrite or Default Lookup ,

It only finished one term , and the route is on rightside  term.

It still has one term no connection.

Thanks,

Charley

Hi Charley,

There are a few things which could affect routing. From the db connectivity (pCell terminals) or access issues due to constraints or rules.

First check the db instance terminals. Select the layout instance and enter the following in the CIW

css()~>terminals~>name

css()~>terminals~>net~>name

Rob.

In addition to Rob's observations, it could also depend on the pin model of the devices. For example, if there are multiple source pins (say) which are not connected inside the device, then the PCell ought to have must-connects between the pins - otherwise it might consider the device as fully connected when one of them is routed. You can check this using this code:

procedure(abPinInfo(@optional (cellView geGetEditCellView()))
  foreach(term cellView~>terminals
    printf("TERM %L NAME %L MUSTJOIN %L PHYSONLY %L INTERFACE %L\n" term term~>name term~>mustJoinTerms term~>physOnly term~>isInterface)
    foreach(pin term~>pins
      printf("  PIN %L NAME %L\n" pin pin~>name)
      foreach(fig pin~>figs
        printf("    LAYER %L CENTER %L\n" fig~>lpp centerBox(fig~>bBox))
      )
    )
  )
  t
)

Use: abPinInfo(car(geGetSelSet())~>master) with the transistor selected.

Andrew

Hi Andrew ,

I select the device and use   Use: abPinInfo(car(geGetSelSet())~>master) 

It print as below:

TERM: db:0x2800999a  NAME "S" MUSTJOIN nll PHYSONLY nil INTERFACE t

  PIN db:0x2800991a  NAME "P__0"

     LAYER ("MET1" "drawing")  CENTER (0.195 5.6)

    LAYER ("MET1" "drawing")  CENTER (1.245 5.6)

  .....

When I select device to check parameter , fingers is 2 , I try to set to 1 , callback show 2 is lower limit.

Do you have any suggestion ?

Thanks,

Charley

Charley,

That shows that there are two metal figures on the S pin, which means that they are considered to be strongly connected (i.e. you only need to connect to one of them). I'm assuming (there's no picture of the layout of the transistor, so it has to be an assumption) that these are the metal pins for the two sources on the multi-finger device; if they are not actually connected within the device, then that's a bug in the PCell/PDK which you'll need to follow up with the foundry; if the pin connectivity model is wrong, then there's little that XL/VSR can do because it is being told that connecting to one of the two MET1 figures is sufficient for the S pin to be fully connected.

Andrew

Hi Andrew,

I got it .

Thanks,

Charley