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Measuring input capacitance of Inverter using SPICE in spectre

AndyWangsh

I'm currently trying to use the SPICE in spectre to measure the input capacitance of the inverter.

However, from the output result in the log, it seems like the input capacitance might possibly not be presented in the way I expected, more specifically, what is m1:n1 representing in nmos?

Why is there a fixed & variable for each capacitor?

Please also include related documentation about the capacitance, thank you!

Below is the spice code for the netlist in gpdk45nm library 

.param w_n=300n
.param w_p=600n
.param l_n=100n
.param l_p=100n

vvdd vdd 0 vdd
vgnd gnd 0 0

M1 out11 in gnd gnd g45n1svt W=W_n L=l_n
M2 out11 in vdd vdd g45p1svt W=W_p L=l_p

.option CAPTAB=1

vin in gnd vdd

Below is the output of the cap table.

Capacitance values computed in info analysis `hspice_CaptabInfo' at T = 25 C.

in : in fixed=0 , variable=0 , sum=0 .

M1:int_d : M1:int_d fixed=40.98 a , variable=758.61 a , sum=799.59 a .

M1:int_s : M1:int_s fixed=40.98 a , variable=591.135 a , sum=632.115 a .

M2:int_d : M2:int_d fixed=89.4 a , variable=211.902 a , sum=301.302 a .

M2:int_s : M2:int_s fixed=89.4 a , variable=340.435 a , sum=429.835 a .

out11 : out11 fixed=0 , variable=0 , sum=0 .

vdd : vdd fixed=0 , variable=645.373 a , sum=645.373 a .

M1.n1 : M1.n1 fixed=81.96 a , variable=418.337 a , sum=500.297 a .

M2.n1 : M2.n1 fixed=178.8 a , variable=172.953 a , sum=351.753 a .

  • This is covered in the documentation. See <SPECTREinstDir>/doc/spectreuser/spectreuser.pdf in the Control Statements chapter. There's a section about info analysis which includes a section Printing the Node Capacitance Table. There is also an option you can add to the info analysis called intrinsic_cap_merge=yes which will merge the capacitances from the internal nodes in the device up to the pins of the device. You can also find the information by running <SPECTRE211>/bin/cdnshelp or <SPECTRE231>/bin/cda (the documentation tool has changed in the latest release) and searching for "captab".

    The M1.n1 and M2.n1 nodes are because the g45n1svt is modelled as a subckt model (actually an inline subckt). The inline device is reported directly, but there's an internal node in the subckt and there's a gate resistor between gate pin and the internal node (n1) to which the gate of the MOS device is connected.

    Andrew

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